Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30350 )
Change subject: mb/google/sarien: Disable pcie interface for wwan ......................................................................
mb/google/sarien: Disable pcie interface for wwan
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the usgae of Sarien choose to only use USB interface but not over pci express, so totally disable pci express root port 12.
BUG=b:1246720 TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10 cyles can still device can be listed under lsusb.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Reviewed-on: https://review.coreboot.org/c/30350 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved EricR Lai: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a8bb342..52840de 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -86,11 +86,6 @@ register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1"
- # PCIe port 12 for M.2 3042 - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[3]" = "11" - register "PcieClkSrcClkReq[3]" = "3" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" @@ -240,7 +235,7 @@ device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c24cd02..47abadc 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -95,11 +95,6 @@ register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1"
- # PCIe port 12 for M.2 3042 - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[0]" = "11" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" @@ -259,7 +254,7 @@ device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1
-
Duncan Laurie (Code Review)