Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76205?usp=email )
Change subject: [WIP] mb/dell: Add Latitude E6410 (Ironlake/Ibex Peak) ......................................................................
[WIP] mb/dell: Add Latitude E6410 (Ironlake/Ibex Peak)
This uses a SMSC MEC5045 EC, which seems to have firmware compatible that is largely similar to the MEC5035 on the E6400. This was based on the Lenovo ThinkPad T410 port.
Untested: Everything
Change-Id: I046c4eba9f69ff50ec1a0f3aacdc536db979025f Signed-off-by: Nicholas Chin nic.c3.14@gmail.com --- A src/mainboard/dell/e6410/Kconfig A src/mainboard/dell/e6410/Kconfig.name A src/mainboard/dell/e6410/Makefile.inc A src/mainboard/dell/e6410/acpi/ec.asl A src/mainboard/dell/e6410/acpi/superio.asl A src/mainboard/dell/e6410/board_info.txt A src/mainboard/dell/e6410/bootblock.c A src/mainboard/dell/e6410/cmos.default A src/mainboard/dell/e6410/cmos.layout A src/mainboard/dell/e6410/data.vbt A src/mainboard/dell/e6410/devicetree.cb A src/mainboard/dell/e6410/dsdt.asl A src/mainboard/dell/e6410/gma-mainboard.ads A src/mainboard/dell/e6410/gpio.c A src/mainboard/dell/e6410/hda_verb.c A src/mainboard/dell/e6410/mainboard.c A src/mainboard/dell/e6410/romstage.c 17 files changed, 529 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/76205/1
diff --git a/src/mainboard/dell/e6410/Kconfig b/src/mainboard/dell/e6410/Kconfig new file mode 100644 index 0000000..c5e3987 --- /dev/null +++ b/src/mainboard/dell/e6410/Kconfig @@ -0,0 +1,41 @@ +if BOARD_DELL_E6410 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_DELL_MEC5035 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_IRONLAKE + select NO_UART_ON_SUPERIO + select SOUTHBRIDGE_INTEL_IBEXPEAK + select SYSTEM_TYPE_LAPTOP + +config CBFS_SIZE + default 0x300000 + +config MAINBOARD_DIR + default "dell/e6410" + +config MAINBOARD_PART_NUMBER + default "Latitude E6410" + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAX_CPUS + int + default 8 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +endif diff --git a/src/mainboard/dell/e6410/Kconfig.name b/src/mainboard/dell/e6410/Kconfig.name new file mode 100644 index 0000000..d0ed01f --- /dev/null +++ b/src/mainboard/dell/e6410/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_E6410 + bool "Latitude E6410" diff --git a/src/mainboard/dell/e6410/Makefile.inc b/src/mainboard/dell/e6410/Makefile.inc new file mode 100644 index 0000000..e1e709a --- /dev/null +++ b/src/mainboard/dell/e6410/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +romstage-y += gpio.c diff --git a/src/mainboard/dell/e6410/acpi/ec.asl b/src/mainboard/dell/e6410/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/dell/e6410/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/e6410/acpi/superio.asl b/src/mainboard/dell/e6410/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/dell/e6410/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/e6410/board_info.txt b/src/mainboard/dell/e6410/board_info.txt new file mode 100644 index 0000000..7eb5a66 --- /dev/null +++ b/src/mainboard/dell/e6410/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2010 diff --git a/src/mainboard/dell/e6410/bootblock.c b/src/mainboard/dell/e6410/bootblock.c new file mode 100644 index 0000000..c72622e --- /dev/null +++ b/src/mainboard/dell/e6410/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <ec/dell/mec5035/mec5035.h> + +void bootblock_mainboard_early_init(void) +{ + mec5035_early_init(); +} diff --git a/src/mainboard/dell/e6410/cmos.default b/src/mainboard/dell/e6410/cmos.default new file mode 100644 index 0000000..ad822d5 --- /dev/null +++ b/src/mainboard/dell/e6410/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/dell/e6410/cmos.layout b/src/mainboard/dell/e6410/cmos.layout new file mode 100644 index 0000000..59b7cce --- /dev/null +++ b/src/mainboard/dell/e6410/cmos.layout @@ -0,0 +1,67 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size +432 2 e 12 hybrid_graphics_mode + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only +12 0 Integrated Only +12 1 Discrete Only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/dell/e6410/data.vbt b/src/mainboard/dell/e6410/data.vbt new file mode 100644 index 0000000..7bac810 --- /dev/null +++ b/src/mainboard/dell/e6410/data.vbt Binary files differ diff --git a/src/mainboard/dell/e6410/devicetree.cb b/src/mainboard/dell/e6410/devicetree.cb new file mode 100644 index 0000000..2d15139 --- /dev/null +++ b/src/mainboard/dell/e6410/devicetree.cb @@ -0,0 +1,81 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/ironlake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as eDP and configure power delays + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" + register "gpu_panel_power_cycle_delay" = "1" + register "gpu_panel_power_up_delay" = "1" + register "gpu_panel_power_down_delay" = "600" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_cpu_backlight" = "0x58d" + register "gpu_pch_backlight" = "0x061a061a" + + chip cpu/intel/model_2065x + device cpu_cluster 0 on ops ironlake_cpu_bus_ops end + end + + device domain 0 on + subsystemid 0x1028 0x040a inherit + ops ironlake_pci_domain_ops + + device pci 00.0 on end # Host bridge + device pci 01.0 off end # PEG + device pci 02.0 on end # VGA controller + + chip southbridge/intel/ibexpeak + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi0_routing" = "2" # EC SCI + register "gpi8_routing" = "1" # EC SMI + + # 0:HDD Bay 1:ODD Bay 4:eSATA Combo Connector 5:Dock eSATA + register "sata_port_map" = "0x33" + + register "gpe0_en" = "0x81010042" + register "alt_gp_smi_en" = "0x0100" + register "gen1_dec" = "0x7c0901" # EC + register "gen2_dec" = "0x3c07e1" # ? + register "gen3_dec" = "0" + register "gen4_dec" = "0" + + register "docking_supported" = "1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 16.0 off end # MEI + device pci 16.2 off end # IDE/SATA + + device pci 19.0 on end # Ethernet + device pci 1a.0 on end # USB2 EHCI + device pci 1b.0 on end # Audio Controller + device pci 1c.0 on end # PCIe Port #1: WWAN mPCIe slot + device pci 1c.1 on end # PCIe Port #2: WLAN mPCIe slot + device pci 1c.2 on end # PCIe Port #3: Ricoh R5U242 SD/Firewire/CardBus + device pci 1c.3 on end # PCIe Port #4: ExpressCard + device pci 1c.4 on end # PCIe Port #5: WPAN + device pci 1c.5 on end # PCIe Port #6: Intel GbE PHY (not PCIe) + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 on end # PCI Bridge + device pci 1f.0 on # PCI-LPC bridge + chip ec/dell/mec5035 + device pnp ff.0 on end + end + end + device pci 1f.2 on end # IDE/SATA + device pci 1f.3 on end # SMBUS + device pci 1f.6 on end # Thermal Subsystem + end + end +end diff --git a/src/mainboard/dell/e6410/dsdt.asl b/src/mainboard/dell/e6410/dsdt.asl new file mode 100644 index 0000000..4a73b6f --- /dev/null +++ b/src/mainboard/dell/e6410/dsdt.asl @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20130325 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/ironlake/acpi/ironlake.asl> + + /* TBD: Remove. */ + Name(\XHCI, 0) + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + #include <northbridge/intel/ironlake/acpi/uncore.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/dell/e6410/gma-mainboard.ads b/src/mainboard/dell/e6410/gma-mainboard.ads new file mode 100644 index 0000000..df70a53 --- /dev/null +++ b/src/mainboard/dell/e6410/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- Muxed between chassis and Dock DP + DP3, -- Dock DP + Analog, -- Muxed between chassis and Dock VGA port + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/e6410/gpio.c b/src/mainboard/dell/e6410/gpio.c new file mode 100644 index 0000000..da34a6e --- /dev/null +++ b/src/mainboard/dell/e6410/gpio.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio8 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio67 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio67 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/dell/e6410/hda_verb.c b/src/mainboard/dell/e6410/hda_verb.c new file mode 100644 index 0000000..5af273d --- /dev/null +++ b/src/mainboard/dell/e6410/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76d5, /* Codec Vendor / Device ID: IDT 92HD81B1C5 */ + 0x1028040a, /* Subsystem ID */ + 10, /* Number of 4 dword sets */ + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x80860101, /* Subsystem ID */ + 3, /* Number of 4 dword sets */ + AZALIA_PIN_CFG(3, 0x04, 0x18560010), + AZALIA_PIN_CFG(3, 0x05, 0x18560020), + AZALIA_PIN_CFG(3, 0x06, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/e6410/mainboard.c b/src/mainboard/dell/e6410/mainboard.c new file mode 100644 index 0000000..3cbf168 --- /dev/null +++ b/src/mainboard/dell/e6410/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_LFP, 2); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/e6410/romstage.c b/src/mainboard/dell/e6410/romstage.c new file mode 100644 index 0000000..afdc391 --- /dev/null +++ b/src/mainboard/dell/e6410/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/ibexpeak/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_557, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_14B, 7 }, + { 1, IF1_557, 7 }, +}; + +void mainboard_pre_raminit(void) +{ +} + +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +}
-
Nicholas Chin (Code Review)