Change in coreboot[master]: amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21883

Change subject: amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx
......................................................................

amd/stoneyridge: Add conversion of PmControl to SLP_TYP_Sx

Convert a value, which may be read from the PmControl register, into
an intended sleep state.  This mimics the Intel function in arch/x86
but uses values specific to the AMD FCH.

Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/sb_util.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/21883/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d506af9..917bd60 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -66,6 +66,14 @@
 #define STONEYRIDGE_ACPI_IO_BASE	CONFIG_STONEYRIDGE_ACPI_IO_BASE
 #define ACPI_PM_EVT_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
 #define ACPI_PM1_CNT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define   SLP_EN			(1 << 13)
+#define   SLP_TYP_SHIFT			10
+#define   SLP_TYP			(7 << SLP_TYP_SHIFT)
+#define     SLP_TYP_S0			0
+#define     SLP_TYP_S1			1
+#define     SLP_TYP_S3			3
+#define     SLP_TYP_S4			4
+#define     SLP_TYP_S5			5
 #define ACPI_PM_TMR_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
 #define ACPI_GPE0_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
 #define ACPI_CPU_CONTROL	(STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
@@ -203,6 +211,7 @@
 void smi_write16(u8 reg, u16 value);
 void smi_write32(u8 reg, u32 value);
 uint16_t pm_acpi_pm_cnt_blk(void);
+int acpi_sleep_from_pm1(uint32_t pm1_cnt);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index bdb199a..acfa41c 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */

+#include <arch/acpi.h>
 #include <soc/southbridge.h>

void pm_write8(u8 reg, u8 value)
@@ -69,3 +70,15 @@
 {
    return pm_read16(PM1_CNT_BLK);
 }
+
+int acpi_sleep_from_pm1(uint32_t pm1_cnt)
+{
+	switch (((pm1_cnt) & SLP_TYP) >> SLP_TYP_SHIFT) {
+	case SLP_TYP_S0: return ACPI_S0;
+	case SLP_TYP_S1: return ACPI_S1;
+	case SLP_TYP_S3: return ACPI_S3;
+	case SLP_TYP_S4: return ACPI_S4;
+	case SLP_TYP_S5: return ACPI_S5;
+	}
+	return -1;
+}