[S] Change in coreboot[master]: soc/intel/broadwell: Allow up to six microcodes in the FIT table

[Angel Pons (Code Review)]

Attention is currently required from: Zhixing Ma, Anil Kumar K, Jérémy Compostella, Selma Bensaid, Nick Vaccaro, Tim Wawrzynczak.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67466 )

Change subject: soc/intel/broadwell: Allow up to six microcodes in the FIT table
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Patch Set 4:

(1 comment)

Patchset:

PS4:
> I made https://review.coreboot. […]
> µcode updates for Haswell come from the `3rdparty/intel-microcode` submodule, whereas µcode updates for Broadwell come from a blob in the `3rdparty/blobs` submodule. The latter has not been updated in a very long time, I wonder if we should make Broadwell use `3rdparty/intel-microcode` as well.

When I added Broadwell's µcode updates to Haswell's CPU code in CB:46942 I didn't disable Haswell's existing µcode updates. Currently, 6 µcode updates are added into coreboot for a Broadwell board: the first 2 come from `3rdparty/intel-microcode` and the last 4 come from the blob in `3rdparty/blobs`.

```
1. [HSW TRAD] µcode, sig 0x000306c3, pf_mask 0x32, 2019-11-12, rev 0x0028
2. [HSW ULTX] µcode, sig 0x00040651, pf_mask 0x72, 2019-11-12, rev 0x0026
3. [HSW ULTX] µcode, sig 0x00040651, pf_mask 0x72, 2014-07-03, rev 0x001c
4. [BDW ULTX] µcode, sig 0x000306d2, pf_mask 0xf2, 2013-12-19, rev 0x-fff7
5. [BDW ULTX] µcode, sig 0x000306d3, pf_mask 0xc0, 2014-07-02, rev 0x-fff0
6. [BDW ULTX] µcode, sig 0x000306d4, pf_mask 0xc0, 2015-02-27, rev 0x001f
```

The 3rd entry is useless, as the 2nd entry is a newer revision of the µcode update for Haswell ULT CPUs. The last 4 entries are at least 7 years old, and I'm pretty sure the intel-microcode repo has newer updates.



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