Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48703 )
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 0 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48703/1
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index f37f37e..5b0621e 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -2,8 +2,6 @@
#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include "thermal.h"
void acpi_create_gnvs(struct global_nvs *gnvs) @@ -16,11 +14,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0;
-#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = CTDP_SENSOR_ID;
gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 666143c..fcafd88 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -3,8 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/nvs.h>
@@ -23,11 +21,6 @@ /* TPM Present */ gnvs->tpmp = 1;
-#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 46a9de7..f40c778 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -395,12 +395,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index aadf3a2..dd8f29f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -164,12 +164,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 4ebe0d5..e188fa6 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -289,16 +289,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0a9b16e..92d1daf 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -77,12 +77,6 @@ struct soc_intel_apollolake_config *cfg; cfg = config_of_soc();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL;
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index fdf7698..e8ef46f 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -20,9 +20,6 @@ #include <soc/pattrs.h> #include <soc/pm.h>
-#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -68,17 +65,6 @@
/* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } }
int acpi_sci_irq(void) diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index e52ea8a..9c4e83a 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -11,7 +11,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <device/pci.h> -#include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> #include <soc/acpi.h> #include <soc/gfx.h> @@ -23,7 +22,6 @@ #include <soc/pm.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h>
#define MWAIT_RES(state, sub_state) \ @@ -71,17 +69,6 @@
/* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } }
int acpi_sci_irq(void) diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9e..dbaade6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 4d4d861..8036210 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -618,17 +618,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 1d4419b..0a09cd4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -20,7 +19,6 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <string.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h>
#include "chip.h" @@ -194,17 +192,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 6d76b66..295a91a 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -257,16 +257,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 30917f3..565dc65 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -6,7 +6,6 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -18,7 +17,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h>
/* @@ -189,16 +187,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 1591953..8494911 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -9,7 +9,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -284,16 +283,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6db7dc1..4de8c5c 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -12,7 +12,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/sgx.h> @@ -29,7 +28,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> #include <device/pci_ops.h>
@@ -167,17 +165,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index f21953d..7f15a96 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -284,16 +283,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index edde09e..bf11bcf 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -654,9 +654,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu();
-#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif
/* Add it to DSDT. */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 739a3c2..102dc08 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -693,12 +693,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu();
-#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32)gnvs);
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48703
to look at the new patch set (#3).
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/raminit.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 23 files changed, 0 insertions(+), 179 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48703/3
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48703
to look at the new patch set (#4).
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/acpi/chromeos-gnvs.c M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 10 insertions(+), 169 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48703/4
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48703
to look at the new patch set (#5).
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/acpi/chromeos-gnvs.c M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 10 insertions(+), 171 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48703/5
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48703
to look at the new patch set (#6).
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/acpi/chromeos-gnvs.c M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 19 files changed, 16 insertions(+), 171 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48703/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48703 )
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
Patch Set 6: Code-Review+1
Kyösti Mälkki has removed Jason Glenesk from this change. ( https://review.coreboot.org/c/coreboot/+/48703 )
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
Removed reviewer Jason Glenesk.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48703 )
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
Patch Set 9: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48703 )
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
Patch Set 9: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48703 )
Change subject: ACPI: Drop redundant ChromeOS setup for GNVS ......................................................................
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/acpi/chromeos-gnvs.c M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 19 files changed, 16 insertions(+), 171 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c index bdd7d69..b1588fa 100644 --- a/src/acpi/chromeos-gnvs.c +++ b/src/acpi/chromeos-gnvs.c @@ -4,12 +4,6 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h>
-/* Remove once implemented on platform code. */ -__weak void *gnvs_chromeos_ptr(struct global_nvs *gnvs) -{ - return NULL; -} - void gnvs_assign_chromeos(void) { chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs()); diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index f37f37e..5b0621e 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -2,8 +2,6 @@
#include <acpi/acpi_gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include "thermal.h"
void acpi_create_gnvs(struct global_nvs *gnvs) @@ -16,11 +14,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0;
-#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = CTDP_SENSOR_ID;
gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 666143c..fcafd88 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -3,8 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <device/device.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/nvs.h>
@@ -23,11 +21,6 @@ /* TPM Present */ gnvs->tpmp = 1;
-#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 4b40e9b..743b32c 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -396,12 +396,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index aadf3a2..dd8f29f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -164,12 +164,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs) { - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 4ebe0d5..616f29e 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -289,16 +288,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0a9b16e..92d1daf 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -77,12 +77,6 @@ struct soc_intel_apollolake_config *cfg; cfg = config_of_soc();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL;
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 72326e7..35b26d3 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -21,9 +21,6 @@ #include <soc/pattrs.h> #include <soc/pm.h>
-#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -69,17 +66,6 @@
/* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } }
int acpi_sci_irq(void) diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 82aff93..bdba583 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -11,7 +11,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <device/pci.h> -#include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> #include <soc/acpi.h> #include <soc/gfx.h> @@ -24,7 +23,6 @@ #include <soc/pm.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h>
#define MWAIT_RES(state, sub_state) \ @@ -72,17 +70,6 @@
/* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } }
int acpi_sci_irq(void) diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 4d4d861..8feae0f 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -13,8 +13,6 @@ #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <string.h> #include <soc/gpio.h> #include <soc/iobp.h> @@ -618,17 +616,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 1d4419b..0a09cd4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -20,7 +19,6 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <string.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h>
#include "chip.h" @@ -194,17 +192,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 6d76b66..f0c0c74 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -9,7 +9,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> @@ -257,16 +256,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 30917f3..565dc65 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -6,7 +6,6 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -18,7 +17,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h>
/* @@ -189,16 +187,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 1591953..8494911 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -9,7 +9,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -284,16 +283,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index a045f2d..0f3136e 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -12,7 +12,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/sgx.h> @@ -30,7 +29,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> #include <device/pci_ops.h>
@@ -168,17 +166,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index f21953d..7f15a96 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -284,16 +283,6 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu();
- if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable;
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0a99d80..a37d298 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -647,6 +647,11 @@ return sizeof(struct global_nvs); }
+void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return &gnvs->chromeos; +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); @@ -659,11 +664,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu();
-#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index c4712ba..39cae48 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -458,6 +458,12 @@ return sizeof(struct global_nvs); }
+/* To build emulation/qemu-q35 with CHROMEOS. */ +void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return 0; +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1f768c2..ae718c1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -690,6 +690,11 @@ return &gnvs->cbmc; }
+void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return &gnvs->chromeos; +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs; @@ -703,12 +708,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu();
-#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - - /* Add it to DSDT. */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32)gnvs);
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Kyösti Mälkki (Code Review)
-
Nico Huber (Code Review)