New subject: Change in ...coreboot[master]: pcengines/apu2: implement POSTCAR_STAGE

19 Apr 2019

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32363
Change subject: /mainboard/pcengines/apu2: implement POSTCAR_STAGE
......................................................................
/mainboard/pcengines/apu2: implement POSTCAR_STAGE
As in [1], POSTCAR_STAGE will be required since October 2019.
[1]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/HNNRR...
Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com
Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf
---
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/Kconfig
M src/mainboard/pcengines/apu2/Makefile.inc
M src/mainboard/pcengines/apu2/OemCustomize.c
A src/mainboard/pcengines/apu2/postcar.c
M src/mainboard/pcengines/apu2/romstage.c
A src/mainboard/pcengines/apu2/state_machine.c
7 files changed, 213 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32363/1

diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 535024a..0178018 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -16,6 +16,7 @@
 #include <AGESA.h>
 #include <spd_bin.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <FchPlatform.h>
 #include <stdlib.h>
@@ -23,7 +24,6 @@
 #include "imc.h"
 #include "hudson.h"
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
@@ -34,8 +34,7 @@
    {AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
    {AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
    {AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config }
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
@@ -56,75 +55,66 @@
    FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;                /* 1 enable, 0 disable TSI Auto Polling */
 }
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
 {
-	AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams =  (FCH_RESET_DATA_BLOCK *) FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-		//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
-		FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-		FchParams->FchReset.SataEnable = hudson_sata_enable();
-		FchParams->FchReset.IdeEnable = hudson_ide_enable();
-		FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->FchReset.Xhci1Enable = FALSE;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+	printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+	//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+	FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
+	FchParams->FchReset.SataEnable = hudson_sata_enable();
+	FchParams->FchReset.IdeEnable = hudson_ide_enable();
+	FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchParams->FchReset.Xhci1Enable = FALSE;
+	printk(BIOS_DEBUG, "Done\n");
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
+{
+	printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-		FchParams->Azalia.AzaliaEnable = AzDisable;
+	FchParams->Azalia.AzaliaEnable = AzDisable;
-		/* Fan Control */
-		oem_fan_control(FchParams);
+	/* Fan Control */
+	oem_fan_control(FchParams);
-		/* XHCI configuration */
-		FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->Usb.Xhci1Enable = FALSE;
+	/* XHCI configuration */
+	FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchParams->Usb.Xhci1Enable = FALSE;
-		/* EHCI configuration */
-		FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
+	/* EHCI configuration */
+	FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
-		if (CONFIG(BOARD_PCENGINES_APU2)) {
-			// Disable EHCI 0 (port 0 to 3)
-			FchParams->Usb.Ehci1Enable = FALSE;
-		} else {
-			// Enable EHCI 0 (port 0 to 3)
-			FchParams->Usb.Ehci1Enable = TRUE;
-		}
+	if (CONFIG(BOARD_PCENGINES_APU2)) {
+		// Disable EHCI 0 (port 0 to 3)
+		FchParams->Usb.Ehci1Enable = FALSE;
+	} else {
+		// Enable EHCI 0 (port 0 to 3)
+		FchParams->Usb.Ehci1Enable = TRUE;
+	}
-		// Enable EHCI 1 (port 4 to 7)
-		// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
-		FchParams->Usb.Ehci2Enable = TRUE;
+	// Enable EHCI 1 (port 4 to 7)
+	// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+	FchParams->Usb.Ehci2Enable = TRUE;
-		/* sata configuration */
-		FchParams->Sata.SataDevSlpPort0 = 0;	// Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
-		FchParams->Sata.SataDevSlpPort1 = 0;
+	/* sata configuration */
+	FchParams->Sata.SataDevSlpPort0 = 0;	// Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+	FchParams->Sata.SataDevSlpPort1 = 0;
-		FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
-		switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
-		case SataRaid:
-		case SataAhci:
-		case SataAhci7804:
-		case SataLegacyIde:
-			FchParams->Sata.SataIdeMode = FALSE;
-			break;
-		case SataIde2Ahci:
-		case SataIde2Ahci7804:
-		default: /* SataNativeIde */
-			FchParams->Sata.SataIdeMode = TRUE;
-			break;
-		}
+	FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+	switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+	case SataRaid:
+	case SataAhci:
+	case SataAhci7804:
+	case SataLegacyIde:
+		FchParams->Sata.SataIdeMode = FALSE;
+		break;
+	case SataIde2Ahci:
+	case SataIde2Ahci7804:
+	default: /* SataNativeIde */
+		FchParams->Sata.SataIdeMode = TRUE;
+		break;
    }
    printk(BIOS_DEBUG, "Done\n");
-
-	return AGESA_SUCCESS;
 }
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 6c3958b..28f9eb8 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -20,7 +20,6 @@
config BOARD_SPECIFIC_OPTIONS
    def_bool y
-	select BINARYPI_LEGACY_WRAPPER
    select CPU_AMD_PI_00730F01
    select NORTHBRIDGE_AMD_PI_00730F01
    select SOUTHBRIDGE_AMD_PI_AVALON
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
index 4e6364e..7824996 100644
--- a/src/mainboard/pcengines/apu2/Makefile.inc
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -14,10 +14,14 @@
 # GNU General Public License for more details.
 #
+romstage-y += state_machine.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
 romstage-y += gpio_ftns.c
+postcar-y += postcar.c
+
+ramstage-y += state_machine.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += OemCustomize.c
 ramstage-y += gpio_ftns.c
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index 700f4c7..7ef7e00 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -14,7 +14,7 @@
  */
#include <AGESA.h>
-#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
@@ -76,25 +76,7 @@
    .DdiLinkList  = NULL,
 };
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
    InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
    InitEarly->PlatformConfig.CStateMode = CStateModeC6;
diff --git a/src/mainboard/pcengines/apu2/postcar.c b/src/mainboard/pcengines/apu2/postcar.c
new file mode 100644
index 0000000..b57ea94
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/postcar.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+
+void late_car_teardown(void)
+{
+	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+	outb(0xEA, 0xCD6);
+	outb(0x1, 0xcd7);
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index bd3c421..a6fe713 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -40,9 +40,11 @@
static void early_lpc_init(void);
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
 {
    u32 val;
+	pci_devfn_t dev;
+	u32 data;
/*
     *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
@@ -57,51 +59,32 @@
hudson_lpc_port80();
-	if (!cpu_init_detectedx && boot_cpu()) {
-		pci_devfn_t dev;
-		u32 data;
+	timestamp_init(timestamp_get());
+	timestamp_add_now(TS_START_ROMSTAGE);
-		timestamp_init(timestamp_get());
-		timestamp_add_now(TS_START_ROMSTAGE);
+	post_code(0x30);
+	early_lpc_init();
-		post_code(0x30);
-		early_lpc_init();
+	hudson_clk_output_48Mhz();
+	post_code(0x31);
-		hudson_clk_output_48Mhz();
-		post_code(0x31);
+	dev = PCI_DEV(0, 0x14, 3);
+	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+	/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
+	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
-		dev = PCI_DEV(0, 0x14, 3);
-		data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
-		/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
-		pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+	/* COM2 on apu5 is reserved so only COM1 should be supported */
+	if ((CONFIG_UART_FOR_CONSOLE == 1) &&
+		!CONFIG(BOARD_PCENGINES_APU5))
+		nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+	else if (CONFIG_UART_FOR_CONSOLE == 0)
+		nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
-		/* COM2 on apu5 is reserved so only COM1 should be supported */
-		if ((CONFIG_UART_FOR_CONSOLE == 1) &&
-			!CONFIG(BOARD_PCENGINES_APU5))
-			nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
-		else if (CONFIG_UART_FOR_CONSOLE == 0)
-			nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
-
-		console_init();
-	}
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x34);
-	report_bist_failure(bist);
+	console_init();
/* Load MPB */
    val = cpuid_eax(1);
    printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
-
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
-
-	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
/* Disable SVI2 controller to wait for command completion */
    val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
@@ -112,27 +95,17 @@
    	val |= (1 << 30);
    	pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
    }
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
-
-	/* FIXME: Detect if TSC frequency changed during raminit? */
-	timestamp_rescale_table(1, 4);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
 }
-void agesa_postcar(struct sysinfo *cb)
-{
-	//PspMboxBiosCmdDramInfo();
-	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+//~ void agesa_postcar(struct sysinfo *cb)
+//~ {
+	//~ //PspMboxBiosCmdDramInfo();
+	//~ post_code(0x41);
+	//~ AGESAWRAPPER(amdinitenv);
-	outb(0xEA, 0xCD6);
-	outb(0x1, 0xcd7);
-}
+	//~ outb(0xEA, 0xCD6);
+	//~ outb(0x1, 0xcd7);
+//~ }
static void early_lpc_init(void)
 {
diff --git a/src/mainboard/pcengines/apu2/state_machine.c b/src/mainboard/pcengines/apu2/state_machine.c
new file mode 100644
index 0000000..4a10df9
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/state_machine.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+#include <binaryPI/FieldAccessors.h>
+
+#include <cbmem.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+
+void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+	backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
+}
+
+void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
+{
+	EmptyHeap();
+}
+
+void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
+{
+}
+
+void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
+{
+	amd_initcpuio();
+}
+
+void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
+{
+	amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
+{
+}
+
+void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
+{
+}
+
+AGESA_STATUS
+AmdGetValue (
+  IN       CONST AGESA_FIELD_NAME name,
+  IN OUT   VOID** value,
+  IN       UINT32 size
+  )
+{
+	AGESA_STATUS status;
+	struct sysinfo cb;
+	AMD_ACCESSOR_PARAMS Params = {};
+
+	agesa_set_interface(&cb);
+	Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr;
+
+	Params.AllocationMethod = ByHost;
+	Params.FieldName = name;
+	Params.FieldValue = *value;
+	Params.FieldSize = size;
+
+	status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params);
+
+	*value = Params.FieldValue;
+	size = Params.FieldSize;
+
+	return status;
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf
Gerrit-Change-Number: 32363
Gerrit-PatchSet: 1
Gerrit-Owner: Krystian Hebel krystian.hebel@3mdeb.com
Gerrit-MessageType: newchange



    

Change in ...coreboot[master]: /mainboard/pcengines/apu2: implement POSTCAR_STAGE