[S] Change in coreboot[main]: soc/intel/alderlake: Hook up PCIe Power Management to option API

[Angel Pons (Code Review)]

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik.

Angel Pons has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81906?usp=email )

Change subject: soc/intel/alderlake: Hook up PCIe Power Management to option API
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Patch Set 10: Code-Review+2

(2 comments)

Patchset:

PS10: 
Technically you

Commit Message:

https://review.coreboot.org/c/coreboot/+/81906/comment/c4efe55c_99aa3213?usp... :
PS10, Line 10: option API.
Ideally, you would want to have per-port options. But I understand that this is not practical given how limited CMOS space is. I would prefer to add a note here describing this limitation.

Alternatively, if you have the root port number, you could complicate things and use `sprintf()` to append the root port number (also differentiate between CPU and PCH RPs). Then, you can just define the options you care about in the CMOS layout (e.g. in-use RPs of a mainboard).