Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA - coreboot-gerrit

1 Nov 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58707 )
Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
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Patch Set 5:
(1 comment)
File src/soc/amd/common/block/lpc/Kconfig:
https://review.coreboot.org/c/coreboot/+/58707/comment/50890b78_0c8e51af 
PS4, Line 23: 	  The LPC SPI DMA controller requires the destination buffers to be 64
...
Adding `help` text for an override is kinda weird. […]
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec
Gerrit-Change-Number: 58707
Gerrit-PatchSet: 5
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Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de
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