Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253
Change subject: Documentation: Document PMH known registers ......................................................................
Documentation: Document PMH known registers
Document what is known of Lenovo's PMH.
Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d94c23e..adfe877 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -54,6 +54,7 @@ - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [PMH](lenovo/pmh.md)
### Sandy Bridge series
diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md new file mode 100644 index 0000000..06c595d --- /dev/null +++ b/Documentation/mainboard/lenovo/pmh.md @@ -0,0 +1,69 @@ +# Lenovo's Power Management Hub + +The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC +to controll power rails and reset lines on the lenovo mainboard. +Starting with Ivy Bridge series, the CPLD was removed and an EC with higher +pincount does the same job. The IO space to configure the PMH is still +the same. + +## PMH access + +The PMH register can be accessed using the IO region: + + IO region address: 0x15e0 + IO region size: 16 + +The IO region has the following layout: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0xc | ADDR_L: Low address into PMH space | ++-------------------+---------------------------------------+ +| 0xd | ADDR_H: High address into PMH space | ++-------------------+---------------------------------------+ +| 0xe | DATA: The data to read/write in PMH | ++-------------------+---------------------------------------+ +``` + +The PMH register space allows to access 512bytes. +The following registers are known: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0x50 | BIT3: dGPU power enable | +| +---------------------------------------+ +| | BIT5: Backlight enable | +| +---------------------------------------+ +| | BIT7: dGPU !reset | ++-------------------+---------------------------------------+ +| 0x51 | BIT0: Trackpoint enable | +| +---------------------------------------+ +| | BIT2: Touchpad enable | ++-------------------+---------------------------------------+ +| 0x60 | BIT3: Dock event enable | ++-------------------+---------------------------------------+ +| 0x62 | BIT0: Ultrabay power enable | ++-------------------+---------------------------------------+ +| 0xc2 | ID: ID of PMH | ++-------------------+---------------------------------------+ +| 0xc3 | REV: Revision of PMH | ++-------------------+---------------------------------------+ +``` + +The revision at 0xc3 seems to increment over time: + +```eval_rst ++-------------------+---------------------------------------+ +| Revision | Mainboard generation | ++-------------------+---------------------------------------+ +| 4 | T520 and T420s | ++-------------------+---------------------------------------+ +| 5 | W530 | ++-------------------+---------------------------------------+ +| 6 | T470p | ++-------------------+---------------------------------------+ +```
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Document PMH known registers ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... File Documentation/mainboard/lenovo/pmh.md:
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... PS1, Line 4: controll control
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Document PMH known registers ......................................................................
Patch Set 1: Code-Review+1
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Document PMH known registers ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... File Documentation/mainboard/lenovo/pmh.md:
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... PS1, Line 5: Starting with Ivy Bridge series, the CPLD was removed and an EC with higher This is not correct. The x1 carbon (gen1) still have the CPLD. http://lunarius.fe80.eu/blog/category/coreboot.html
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Document PMH known registers ......................................................................
Patch Set 1: Code-Review-1
Hello Alexander Couzens, Arthur Heymans, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32253
to look at the new patch set (#2).
Change subject: tDocumentation: Document PMH known registers ......................................................................
tDocumentation: Document PMH known registers
Document what is known of Lenovo's PMH.
Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/2
Hello Alexander Couzens, Arthur Heymans, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32253
to look at the new patch set (#3).
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Documentation: Add lenovo's PMH known registers
Document what is known of Lenovo's PMH.
Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... File Documentation/mainboard/lenovo/pmh.md:
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... PS1, Line 4: controll
control
Done
https://review.coreboot.org/#/c/32253/1/Documentation/mainboard/lenovo/pmh.m... PS1, Line 5: Starting with Ivy Bridge series, the CPLD was removed and an EC with higher
This is not correct. The x1 carbon (gen1) still have the CPLD. http://lunarius.fe80. […]
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Patch Set 4: Code-Review+1
looks good to me; haven't verified the offsets and bits though
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32253/4/Documentation/mainboard/lenovo/pmh.m... File Documentation/mainboard/lenovo/pmh.md:
https://review.coreboot.org/#/c/32253/4/Documentation/mainboard/lenovo/pmh.m... PS4, Line 31: 512 at least the PMH/Thinker1 can address 10bit(1024bytes) with the SPI based protocol. So far only registers with 9bit(512bytes) has been seen so far.
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Patch Set 4:
LGTM, except the 512bytes registers. Not sure if we should state the 10bit register space there, as we only saw 9bit registers so far.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Patch Set 4: Code-Review+1
Attention is currently required from: Patrick Rudolph, Alexander Couzens. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32253 )
Change subject: Documentation: Add lenovo's PMH known registers ......................................................................
Patch Set 4:
(1 comment)
File Documentation/mainboard/lenovo/pmh.md:
https://review.coreboot.org/c/coreboot/+/32253/comment/6396f6a8_02529a57 PS4, Line 31: 512
at least the PMH/Thinker1 can address 10bit(1024bytes) with the SPI based protocol. […]
so should this be updated to 1024bytes or should we merge this as it is right now? i'd like to have this documentation in tree
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Alexander Couzens (Code Review) -
Angel Pons (Code Review)
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Arthur Heymans (Code Review)
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Felix Held (Code Review)
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Patrick Rudolph (Code Review)