[M] Change in coreboot[master]: src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logic

[Jérémy Compostella (Code Review)]

Attention is currently required from: Bora Guvendik, Hannah Williams, Cliff Huang, Tarun Tuli, Subrata Banik, Nick Vaccaro.

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72421 )

Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logic
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Patch Set 2:

(2 comments)

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/72421/comment/b9fed257_e27a0b38 
PS2, Line 264: 	/* for enable pin:
This is clearly not a one liner comment and therefore the syntax you used is incorrect. I also think that:
1. The explanation could use a little bit more text
2. This should actually be the function comment instead of an in-function comment.

Here is what I suggest.
```
/*
 * Depending on the board configuration we use either the "enable" or the
 * "reset" pin to detect the status of the device. The logic for each pin is
 * detailed below.
 *
 * 1. For the "enable" pin:
 * | polarity    | tx value | get_tx_gpio() | State |
 * |-------------+----------+---------------+-------|
 * | active high |     0    |     0         |   0   |
 * | active high |     1    |     1(active) |   1   |
 * | active low  |     0    |     1(active) |   1   |
 * | active low  |     1    |     0         |   0   |
 *
 * 2. For the the "reset" pin:
 * | polarity    | tx value | get_tx_gpio() | State |
 * |-------------+----------+---------------+-------|
 * | active high |     0    |     0         |   1   |
 * | active high |     1    |     1(active) |   0   |
 * | active low  |     0    |     1(active) |   0   |
 * | active low  |     1    |     0         |   1   |
 */

```

https://review.coreboot.org/c/coreboot/+/72421/comment/ed2d6439_fbf29ceb 
PS2, Line 286: 		acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP);
Can't we use `acpigen_write_not(LOCAL0_OP, LOCAL0_OP)` instead ?