Change in coreboot[master]: soc/intel/common/sgx: Define and use soc_fill_sgx_param()

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21528

Change subject: soc/intel/common/sgx: Define and use soc_fill_sgx_param()
......................................................................

soc/intel/common/sgx: Define and use soc_fill_sgx_param()

To remove chip.h dependency from SGX common code
- Create API soc_fill_sgx_param() and use it in sgx.c
- Implement same API for skylake/kabylake
- define sgx_param_t structure

Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0
Signed-off-by: Pratik Prajapati 
---
M src/soc/intel/common/block/include/intelblocks/sgx.h
M src/soc/intel/common/block/sgx/sgx.c
M src/soc/intel/skylake/cpu.c
3 files changed, 31 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/21528/1

diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h
index efcad61..1b341f5 100644
--- a/src/soc/intel/common/block/include/intelblocks/sgx.h
+++ b/src/soc/intel/common/block/include/intelblocks/sgx.h
@@ -16,6 +16,10 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SGX_H
 #define SOC_INTEL_COMMON_BLOCK_SGX_H

+struct sgx_param_t {
+	uint8_t enable;
+};
+
 /*
  * Lock SGX memory.
  * CPU specific code needs to provide the implementation.
@@ -34,4 +38,8 @@
  */
 void sgx_configure(void);

+/* SOC specific API to get SGX params.
+ * returns 0, if able to get SGX params; otherwise returns -1 */
+int soc_fill_sgx_param(struct sgx_param_t *sgx_param);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_SGX_H */
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index ec1b638..072b922 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -15,7 +15,6 @@

#include <assert.h>
 #include <console/console.h>
-#include <chip.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/microcode.h>
@@ -40,16 +39,14 @@
    msr_t prmrr_base;
    msr_t prmrr_mask;
    msr_t msr;
-	device_t dev = SA_DEV_ROOT;
-	assert(dev != NULL);
-	config_t *conf = dev->chip_info;
+	struct sgx_param_t sgx_param;

-	if (!conf) {
-		printk(BIOS_ERR, "SGX: failed to get chip_info\n");
+	if (soc_fill_sgx_param(&sgx_param) < 0) {
+		printk(BIOS_ERR, "SGX: failed to get sgx_param from soc\n");
    	return;
    }

-	if (!conf->sgx_enable || !is_sgx_supported())
+	if (!sgx_param.enable || !is_sgx_supported())
    	return;

/* PRMRR base and mask are read from the UNCORE PRMRR MSRs
@@ -160,17 +157,15 @@

void sgx_configure(void)
 {
-	device_t dev = SA_DEV_ROOT;
-	assert(dev != NULL);
-	config_t *conf = dev->chip_info;
    const void *microcode_patch = intel_mp_current_microcode();
+	struct sgx_param_t sgx_param;

-	if (!conf) {
-		printk(BIOS_ERR, "SGX: failed to get chip_info\n");
+	if (soc_fill_sgx_param(&sgx_param) < 0) {
+		printk(BIOS_ERR, "SGX: failed to get sgx_param from soc\n");
    	return;
    }

-	if (!conf->sgx_enable || !is_sgx_supported() || !is_prmrr_set()) {
+	if (!sgx_param.enable || !is_sgx_supported() || !is_prmrr_set()) {
    	printk(BIOS_ERR, "SGX: pre-conditions not met\n");
    	return;
    }
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 1e12c65..811f57e 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -504,3 +504,18 @@
    	wrmsr(MSR_LT_LOCK_MEMORY, msr);
    }
 }
+
+int soc_fill_sgx_param(struct sgx_param_t *sgx_param)
+{
+	device_t dev = SA_DEV_ROOT;
+	assert(dev != NULL);
+	config_t *conf = dev->chip_info;
+
+	if (!conf) {
+		printk(BIOS_ERR, "Failed to get chip_info for SGX param\n");
+		return -1;
+	}
+
+	sgx_param->enable = conf->sgx_enable;
+	return 0;
+}