Julius Werner (jwerner@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11913
-gerrit
commit d76c1e2f0e80cc4e6318584e07d8dcdff124ba75 Author: Furquan Shaikh furquan@google.com Date: Thu Oct 15 15:50:30 2015 -0700
arm64: Remove cpu intialization through device-tree
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree.
Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh furquan@google.com --- src/arch/arm64/Makefile.inc | 1 - src/arch/arm64/c_entry.c | 75 ++++++++++ src/arch/arm64/cpu_ramstage.c | 204 ---------------------------- src/arch/arm64/include/armv8/arch/cpu.h | 34 +---- src/drivers/gic/gic.c | 1 + src/mainboard/google/rush/devicetree.cb | 1 - src/mainboard/google/rush_ryu/devicetree.cb | 2 - src/mainboard/google/smaug/devicetree.cb | 1 - src/soc/nvidia/tegra132/ramstage.c | 15 ++ src/soc/nvidia/tegra132/soc.c | 56 ++------ src/soc/nvidia/tegra210/ramstage.c | 6 + src/soc/nvidia/tegra210/soc.c | 54 ++------ 12 files changed, 121 insertions(+), 329 deletions(-)
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index b4ee3a5..8bcad75 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -131,7 +131,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) ramstage-y += c_entry.c ramstage-y += stages.c ramstage-y += div0.c -ramstage-y += cpu_ramstage.c ramstage-y += eabi_compat.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index deef83d..f26ed92 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -15,8 +15,11 @@
#include <arch/cache.h> #include <arch/cpu.h> +#include <arch/lib_helpers.h> #include <arch/mmu.h> #include <arch/stages.h> +#include <gic.h> + #include "cpu-internal.h"
void __attribute__((weak)) arm64_soc_init(void) @@ -42,10 +45,82 @@ static void seed_stack(void) *slot++ = 0xdeadbeefdeadbeefULL; }
+/* Set up default SCR values. */ +static void el3_init(void) +{ + uint32_t scr; + + if (get_current_el() != EL3) + return; + + scr = raw_read_scr_el3(); + /* Default to non-secure EL1 and EL0. */ + scr &= ~(SCR_NS_MASK); + scr |= SCR_NS_ENABLE; + /* Disable IRQ, FIQ, and external abort interrupt routing. */ + scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); + scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; + /* Enable HVC */ + scr &= ~(SCR_HVC_MASK); + scr |= SCR_HVC_ENABLE; + /* Disable SMC */ + scr &= ~(SCR_SMC_MASK); + scr |= SCR_SMC_DISABLE; + /* Disable secure instruction fetches. */ + scr &= ~(SCR_SIF_MASK); + scr |= SCR_SIF_DISABLE; + /* All lower exception levels 64-bit by default. */ + scr &= ~(SCR_RW_MASK); + scr |= SCR_LOWER_AARCH64; + /* Disable secure EL1 access to secure timer. */ + scr &= ~(SCR_ST_MASK); + scr |= SCR_ST_DISABLE; + /* Don't trap on WFE or WFI instructions. */ + scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); + scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; + raw_write_scr_el3(scr); + isb(); +} + +void __attribute__((weak)) arm64_arch_timer_init(void) +{ + /* Default weak implementation does nothing. */ +} + static void arm64_init(void) { seed_stack(); + + /* Set up default SCR values. */ + el3_init(); + + /* Initialize the GIC. */ + gic_init(); + + /* + * Disable coprocessor traps to EL3: + * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR + * and EL2/EL1 access to CPACR_EL1. + * TTA [20] = 0, disable traps for trace register access from any EL. + * TFP [10] = 0, disable traps for floating-point instructions from any + * EL. + */ + raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | + CPTR_EL3_TFP_DISABLE); + + /* + * Allow FPU accesses: + * FPEN [21:20] = 3, disable traps for floating-point instructions from + * EL0/EL1. + * TTA [28] = 0, disable traps for trace register access from EL0/EL1. + */ + raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE); + + /* Arch Timer init: setup cntfrq per CPU */ + arm64_arch_timer_init(); + arm64_soc_init(); + main(); }
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c deleted file mode 100644 index c94c26f..0000000 --- a/src/arch/arm64/cpu_ramstage.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <arch/cache.h> -#include <arch/cpu.h> -#include <arch/lib_helpers.h> -#include <cpu/cpu.h> -#include <console/console.h> -#include <gic.h> -#include <timer.h> -#include "cpu-internal.h" - -static struct cpu_info cpu_info; - -void __attribute__((weak)) arm64_arch_timer_init(void) -{ - /* Default weak implementation does nothing. */ -} - -static inline void cpu_disable_dev(device_t dev) -{ - dev->enabled = 0; -} - -static struct cpu_driver *locate_cpu_driver(uint32_t midr) -{ - struct cpu_driver *cur; - - for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) { - const struct cpu_device_id *id_table = cur->id_table; - - for (; id_table->midr != CPU_ID_END; id_table++) { - if (id_table->midr == midr) - return cur; - } - } - return NULL; -} - -static int cpu_set_device_operations(device_t dev) -{ - uint32_t midr; - struct cpu_driver *driver; - - midr = raw_read_midr_el1(); - driver = locate_cpu_driver(midr); - - if (driver == NULL) { - printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr); - return -1; - } - dev->ops = driver->ops; - return 0; -} - -/* Set up default SCR values. */ -static void el3_init(void) -{ - uint32_t scr; - - if (get_current_el() != EL3) - return; - - scr = raw_read_scr_el3(); - /* Default to non-secure EL1 and EL0. */ - scr &= ~(SCR_NS_MASK); - scr |= SCR_NS_ENABLE; - /* Disable IRQ, FIQ, and external abort interrupt routing. */ - scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); - scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; - /* Enable HVC */ - scr &= ~(SCR_HVC_MASK); - scr |= SCR_HVC_ENABLE; - /* Disable SMC */ - scr &= ~(SCR_SMC_MASK); - scr |= SCR_SMC_DISABLE; - /* Disable secure instruction fetches. */ - scr &= ~(SCR_SIF_MASK); - scr |= SCR_SIF_DISABLE; - /* All lower exception levels 64-bit by default. */ - scr &= ~(SCR_RW_MASK); - scr |= SCR_LOWER_AARCH64; - /* Disable secure EL1 access to secure timer. */ - scr &= ~(SCR_ST_MASK); - scr |= SCR_ST_DISABLE; - /* Don't trap on WFE or WFI instructions. */ - scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); - scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; - raw_write_scr_el3(scr); - isb(); -} - -static void init_this_cpu(void) -{ - struct cpu_info *ci = &cpu_info; - device_t dev = ci->cpu; - - cpu_set_device_operations(dev); - - printk(BIOS_DEBUG, "CPU%x: MPIDR: %llx\n", ci->id, ci->mpidr); - - /* Initialize the GIC. */ - gic_init(); - - /* - * Disable coprocessor traps to EL3: - * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR - * and EL2/EL1 access to CPACR_EL1. - * TTA [20] = 0, disable traps for trace register access from any EL. - * TFP [10] = 0, disable traps for floating-point instructions from any - * EL. - */ - raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | - CPTR_EL3_TFP_DISABLE); - - /* - * Allow FPU accesses: - * FPEN [21:20] = 3, disable traps for floating-point instructions from - * EL0/EL1. - * TTA [28] = 0, disable traps for trace register access from EL0/EL1. - */ - raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE); - - /* Arch Timer init: setup cntfrq per CPU */ - arm64_arch_timer_init(); - - if (dev->ops != NULL && dev->ops->init != NULL) { - dev->initialized = 1; - printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); - dev->ops->init(dev); - } -} - -/* Fill in cpu_info structures according to device tree. */ -static void init_cpu_info(struct bus *bus) -{ - device_t cur; - - for (cur = bus->children; cur != NULL; cur = cur->sibling) { - struct cpu_info *ci; - unsigned int id = cur->path.cpu.id; - - if (cur->path.type != DEVICE_PATH_CPU) - continue; - - /* IDs are currently mapped 1:1 with logical CPU numbers. */ - if (id != 0) { - printk(BIOS_WARNING, - "CPU id %x too large. Disabling.\n", id); - cpu_disable_dev(cur); - continue; - } - - ci = &cpu_info; - if (ci->cpu != NULL) { - printk(BIOS_WARNING, - "Duplicate ID %x in device tree.\n", id); - cpu_disable_dev(cur); - } - - ci->cpu = cur; - ci->id = cur->path.cpu.id; - } -} - -void arch_initialize_cpu(device_t cluster) -{ - struct bus *bus; - - if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) { - printk(BIOS_ERR, - "CPU init failed. Device is not a CPU_CLUSTER: %s\n", - dev_path(cluster)); - return; - } - - bus = cluster->link_list; - - /* Check if no children under this device. */ - if (bus == NULL) - return; - - el3_init(); - - /* Initialize the cpu_info structures. */ - init_cpu_info(bus); - - /* Send it the init action. */ - init_this_cpu(); -} diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 778909d..fdc34e5 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -18,36 +18,6 @@
#define asmlinkage
-#if !defined(__PRE_RAM__) -#include <arch/barrier.h> -#include <arch/mpidr.h> -#include <device/device.h> - -enum { - CPU_ID_END = 0x00000000, -}; - -struct cpu_device_id { - uint32_t midr; -}; - -struct cpu_driver { - /* This is excessive as init() is the only one called. */ - struct device_operations *ops; - const struct cpu_device_id *id_table; -}; - -struct cpu_info { - device_t cpu; - unsigned int id; - uint64_t mpidr; -}; - -/* Initialize CPU0 under the DEVICE_PATH_CPU_CLUSTER cluster. */ -void arch_initialize_cpu(device_t cluster); - -#endif /* !__PRE_RAM__ */ - static inline unsigned int smp_processor_id(void) { return 0; }
/* @@ -63,4 +33,8 @@ void arm64_cpu_startup(void); */ void arm64_arch_timer_init(void);
+#if !defined(__PRE_RAM__) +struct cpu_driver { }; +#endif + #endif /* __ARCH_CPU_H__ */ diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c index 622aaff..80e98eb 100644 --- a/src/drivers/gic/gic.c +++ b/src/drivers/gic/gic.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <console/console.h> #include <gic.h> +#include <stddef.h> #include "gic.h"
enum { diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb index 40c4ec3..6b3e148 100644 --- a/src/mainboard/google/rush/devicetree.cb +++ b/src/mainboard/google/rush/devicetree.cb @@ -15,7 +15,6 @@
chip soc/nvidia/tegra132 device cpu_cluster 0 on - device cpu 0 on end end
register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb index 5caa6f6..4245444 100644 --- a/src/mainboard/google/rush_ryu/devicetree.cb +++ b/src/mainboard/google/rush_ryu/devicetree.cb @@ -15,8 +15,6 @@
chip soc/nvidia/tegra132 device cpu_cluster 0 on - device cpu 0 on end - device cpu 1 on end end
register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index e7f8647..5d7bf86 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -15,7 +15,6 @@
chip soc/nvidia/tegra210 device cpu_cluster 0 on - device cpu 0 on end end
register "display_controller" = "TEGRA_ARM_DISPLAYA" diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index 64b61e9..ca9cec4 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -16,8 +16,18 @@ #include <arch/stages.h> #include <soc/addressmap.h> #include <soc/clock.h> +#include <soc/mc.h> #include <soc/mmu_operations.h>
+static void lock_down_vpr(void) +{ + struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; + + write32(®s->video_protect_bom, 0); + write32(®s->video_protect_size_mb, 0); + write32(®s->video_protect_reg_ctrl, 1); +} + void arm64_soc_init(void) { trustzone_region_init(); @@ -25,4 +35,9 @@ void arm64_soc_init(void) tegra132_mmu_init();
clock_cpu0_config(); + + clock_init_arm_generic_timer(); + + /* Lock down VPR */ + lock_down_vpr(); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 8eabd39..40889a7 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -26,7 +26,6 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/cpu.h> -#include <soc/mc.h> #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> @@ -55,38 +54,11 @@ static void soc_read_resources(device_t dev) ram_resource(dev, index++, begin * KiB, size * KiB); }
-static void lock_down_vpr(void) -{ - struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; - - write32(®s->video_protect_bom, 0); - write32(®s->video_protect_size_mb, 0); - write32(®s->video_protect_reg_ctrl, 1); -} - -static void soc_init(device_t dev) -{ - clock_init_arm_generic_timer(); - - arch_initialize_cpu(dev); - - /* Lock down VPR */ - lock_down_vpr(); - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return; - - if (display_init_required()) - display_startup(dev); - else - printk(BIOS_INFO, "Skipping display init.\n"); -} - static struct device_operations soc_ops = { .read_resources = soc_read_resources, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = soc_init, + .init = DEVICE_NOOP, .scan_bus = NULL, };
@@ -94,6 +66,14 @@ static void enable_tegra132_dev(device_t dev) { if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; + + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) + display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); }
static void tegra132_init(void *chip_info) @@ -114,24 +94,6 @@ struct chip_operations soc_nvidia_tegra132_ops = { .enable_dev = enable_tegra132_dev, };
-static void tegra132_cpu_init(device_t cpu) -{ -} - -static const struct cpu_device_id ids[] = { - { 0x4e0f0000 }, - { CPU_ID_END }, -}; - -static struct device_operations cpu_dev_ops = { - .init = tegra132_cpu_init, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = ids, -}; - static void enable_plld(void *unused) { /* diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index f55c256..5c37510 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -19,6 +19,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> +#include <soc/mtc.h>
void arm64_arch_timer_init(void) { @@ -54,4 +55,9 @@ void arm64_soc_init(void) trustzone_region_init();
tegra210_mmu_init(); + + clock_init_arm_generic_timer(); + + if (tegra210_run_mtc() != 0) + printk(BIOS_ERR, "MTC: No training data.\n"); } diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index bcbef49..1071d68 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -27,7 +27,6 @@ #include <soc/clock.h> #include <soc/cpu.h> #include <soc/mc.h> -#include <soc/mtc.h> #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> @@ -58,30 +57,11 @@ static void soc_read_resources(device_t dev) ram_resource(dev, index++, begin * KiB, size * KiB); }
-static void soc_init(device_t dev) -{ - clock_init_arm_generic_timer(); - - arch_initialize_cpu(dev); - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return; - - if (display_init_required()) - display_startup(dev); - else - printk(BIOS_INFO, "Skipping display init.\n"); -} - -static void soc_noop(device_t dev) -{ -} - static struct device_operations soc_ops = { .read_resources = soc_read_resources, - .set_resources = soc_noop, - .enable_resources = soc_noop, - .init = soc_init, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, .scan_bus = NULL, };
@@ -89,6 +69,14 @@ static void enable_tegra210_dev(device_t dev) { if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; + + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) + display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); }
static void tegra210_init(void *chip_info) @@ -111,26 +99,6 @@ struct chip_operations soc_nvidia_tegra210_ops = { .enable_dev = enable_tegra210_dev, };
-static void tegra210_cpu_init(device_t cpu) -{ - if (tegra210_run_mtc() != 0) - printk(BIOS_ERR, "MTC: No training data.\n"); -} - -static const struct cpu_device_id ids[] = { - { 0x411fd071 }, - { CPU_ID_END }, -}; - -static struct device_operations cpu_dev_ops = { - .init = tegra210_cpu_init, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = ids, -}; - static void enable_plld(void *unused) { /*
-
Julius Werner