Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47112 )
Change subject: nb/intel: Use `read_option_u8` wrapper ......................................................................
nb/intel: Use `read_option_u8` wrapper
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 11 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47112/1
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 102af1c..3beea47 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -116,11 +116,11 @@ sysinfo->ggc = 0x0002; else { /* 4 for 32MB, default if not set in CMOS */ - u8 gfxsize = 4; + u8 gfxsize = read_option_u8("gfx_uma_size", 4);
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ - get_option(&gfxsize, "gfx_uma_size"); + /* Handle invalid CMOS settings */ /* Only allow settings between 32MB and 352MB */ gfxsize = MIN(MAX(gfxsize, 4), 12); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b..0c87501 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -149,8 +149,7 @@ pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
/* vram size from CMOS option */ - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) - gfxsize = 2; /* 2 for 8MB */ + gfxsize = read_option_u8("gfx_uma_size", 2) /* 2 for 8MB */ /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 118d02c..258c698 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -706,15 +706,10 @@
static void gma_func1_init(struct device *dev) { - u8 val; - if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- if (get_option(&val, "tft_brightness") == CB_SUCCESS) - pci_write_config8(dev, 0xf4, val); - else - pci_write_config8(dev, 0xf4, 0xff); + pci_write_config8(dev, 0xf4, read_option_u8("tft_brightness", 0xff)); }
static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 05323f1..acb1ae5 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3636,10 +3636,7 @@ MCHBAR16(0x1170) = 0xb880; MCHBAR8_AND_OR(0x1210, 0, 0x84);
- if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 0 for 32MB */ - gfxsize = 0; - } + gfxsize = read_option_u8("gfx_uma_size", 0); /* 0 for 32MB */
ggc = 0xb00 | ((gfxsize + 5) << 4);
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..0a96471 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,8 +25,7 @@ pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
/* Fetch VRAM size from CMOS option */ - if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) - reg8 = 0; /* 0 for 8MB */ + reg8 = read_option_u8("gfx_uma_size", 0); /* 0 for 8MB */
/* Ensure the setting is valid */ if (reg8 > 6) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..22c4b20 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -87,10 +87,9 @@
printk(BIOS_DEBUG, "Initializing Graphics...\n");
- if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ - gfxsize = 0; - } + /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ + gfxsize = read_option_u8("gfx_uma_size", 0); + reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; reg16 |= (gfxsize + 1) << 3; diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 279a38f..41a3f07 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -39,9 +39,8 @@ /* Enable internal GFX */ pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
- /* Set preallocated IGD size from CMOS */ - u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */ - get_option(&gfxsize, "gfx_uma_size"); + /* Set preallocated IGD size from CMOS, or default to 64 MiB */ + u8 gfxsize = read_option_u8("gfx_uma_size", 6); if (gfxsize > 12) gfxsize = 6; /* Need at least 4M for cbmem_top alignment */
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47112 )
Change subject: nb/intel: Use `read_option_u8` wrapper ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47112/2/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/47112/2/src/northbridge/intel/i945/... PS2, Line 152: gfxsize = read_option_u8("gfx_uma_size", 2) /* 2 for 8MB */ hell you doofus, forgot the ;
Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47112
to look at the new patch set (#3).
Change subject: nb/intel: Use `read_option_u8` wrapper ......................................................................
nb/intel: Use `read_option_u8` wrapper
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 11 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47112/3
Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47112
to look at the new patch set (#4).
Change subject: nb/intel: Use get_int_option() ......................................................................
nb/intel: Use get_int_option()
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 11 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47112/4
Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47112 )
Change subject: nb/intel: Use get_int_option() ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47112 )
Change subject: nb/intel: Use get_int_option() ......................................................................
Patch Set 6:
(1 comment)
File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/47112/comment/d1124f15_f76e32fa PS2, Line 152: gfxsize = read_option_u8("gfx_uma_size", 2) /* 2 for 8MB */
hell you doofus, forgot the ;
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47112 )
Change subject: nb/intel: Use get_int_option() ......................................................................
nb/intel: Use get_int_option()
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c 7 files changed, 11 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index f4a0e0c..f7bdb28 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -116,11 +116,11 @@ sysinfo->ggc = 0x0002; else { /* 4 for 32MB, default if not set in CMOS */ - u8 gfxsize = 4; + u8 gfxsize = get_int_option("gfx_uma_size", 4);
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ - get_option(&gfxsize, "gfx_uma_size"); + /* Handle invalid CMOS settings */ /* Only allow settings between 32MB and 352MB */ gfxsize = MIN(MAX(gfxsize, 4), 12); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 3c5917b..b9c9441 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -149,8 +149,7 @@ pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
/* vram size from CMOS option */ - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) - gfxsize = 2; /* 2 for 8MB */ + gfxsize = get_int_option("gfx_uma_size", 2); /* 2 for 8MB */ /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e00026a..8aa722c 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -707,15 +707,10 @@
static void gma_func1_init(struct device *dev) { - u8 val; - if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- if (get_option(&val, "tft_brightness") == CB_SUCCESS) - pci_write_config8(dev, 0xf4, val); - else - pci_write_config8(dev, 0xf4, 0xff); + pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff)); }
static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 4d8fa13..8f4aba5 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3102,10 +3102,7 @@ mchbar_write16(0x1170, 0xb880); mchbar_clrsetbits8(0x1210, ~0, 0x84);
- if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 0 for 32MB */ - gfxsize = 0; - } + gfxsize = get_int_option("gfx_uma_size", 0); /* 0 for 32MB */
ggc = 0xb00 | ((gfxsize + 5) << 4);
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index a2bbaa0..df7dcb3 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,8 +25,7 @@ pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
/* Fetch VRAM size from CMOS option */ - if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) - reg8 = 0; /* 0 for 8MB */ + reg8 = get_int_option("gfx_uma_size", 0); /* 0 for 8MB */
/* Ensure the setting is valid */ if (reg8 > 6) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 922c4b7..51b8512 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -86,10 +86,9 @@
printk(BIOS_DEBUG, "Initializing Graphics...\n");
- if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ - gfxsize = 0; - } + /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ + gfxsize = get_int_option("gfx_uma_size", 0); + reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; reg16 |= (gfxsize + 1) << 3; diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index de261bd..1de9e28 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -38,9 +38,8 @@ /* Enable internal GFX */ pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
- /* Set preallocated IGD size from CMOS */ - u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */ - get_option(&gfxsize, "gfx_uma_size"); + /* Set preallocated IGD size from CMOS, or default to 64 MiB */ + u8 gfxsize = get_int_option("gfx_uma_size", 6); if (gfxsize > 12) gfxsize = 6; /* Need at least 4M for cbmem_top alignment */
-
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Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)