Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68188 )
Change subject: [WIP] mb/asrock/z97_extreme6: Add new mainboard ......................................................................
[WIP] mb/asrock/z97_extreme6: Add new mainboard
Not even boot-tested.
Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/z97_extreme6/Kconfig A src/mainboard/asrock/z97_extreme6/Kconfig.name A src/mainboard/asrock/z97_extreme6/Makefile.inc A src/mainboard/asrock/z97_extreme6/acpi/ec.asl A src/mainboard/asrock/z97_extreme6/acpi/platform.asl A src/mainboard/asrock/z97_extreme6/acpi/superio.asl A src/mainboard/asrock/z97_extreme6/board_info.txt A src/mainboard/asrock/z97_extreme6/bootblock.c A src/mainboard/asrock/z97_extreme6/data.vbt A src/mainboard/asrock/z97_extreme6/devicetree.cb A src/mainboard/asrock/z97_extreme6/dsdt.asl A src/mainboard/asrock/z97_extreme6/gma-mainboard.ads A src/mainboard/asrock/z97_extreme6/gpio.c A src/mainboard/asrock/z97_extreme6/hda_verb.c A src/mainboard/asrock/z97_extreme6/romstage.c 15 files changed, 525 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/68188/1
diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig new file mode 100644 index 0000000..d969822 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig @@ -0,0 +1,26 @@ +if BOARD_ASROCK_Z97_EXTREME6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config CBFS_SIZE + default 0x200000 + +config MAINBOARD_DIR + default "asrock/z97_extreme6" + +config MAINBOARD_PART_NUMBER + default "Z97 Extreme6" + +endif diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig.name b/src/mainboard/asrock/z97_extreme6/Kconfig.name new file mode 100644 index 0000000..1a75148 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_Z97_EXTREME6 + bool "Z97 Extreme6" diff --git a/src/mainboard/asrock/z97_extreme6/Makefile.inc b/src/mainboard/asrock/z97_extreme6/Makefile.inc new file mode 100644 index 0000000..ec8ca22 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z97_extreme6/acpi/ec.asl b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z97_extreme6/acpi/platform.asl b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl new file mode 100644 index 0000000..7da03bf --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/z97_extreme6/acpi/superio.asl b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z97_extreme6/board_info.txt b/src/mainboard/asrock/z97_extreme6/board_info.txt new file mode 100644 index 0000000..bd01474 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z97%20extreme6/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c new file mode 100644 index 0000000..6d397ff --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/bootblock.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) + +/* FIXME: fill this in */ +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x24, 0xfc); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x02); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + //pnp_set_logical_device(ACPI_DEV); + //pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z97_extreme6/data.vbt b/src/mainboard/asrock/z97_extreme6/data.vbt new file mode 100644 index 0000000..6a73a26 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb new file mode 100644 index 0000000..5d9e7ff --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -0,0 +1,117 @@ +chip northbridge/intel/haswell + + # This mainboard has DVI-I + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe graphics + device pci 01.1 on end # FIXME: figure out the PCIe mux spam + device pci 01.2 on end # FIXME: figure out the PCIe mux spam + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" # Super I/O HWM + register "sata_port_map" = "0x3f" + register "gpe0_en_1" = "0x40002246" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 on end # Intel GbE through I218-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: Maybe M.2? + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3: Realtek RTL8111 GbE NIC + device pci 1c.3 on end # RP #4: ASM1184e 4-Port PCIe Switch + device pci 1c.4 on end # RP #5 + device pci 1c.5 on end # RP #6 + device pci 1c.6 on end # RP #7: ASM1042A USB 3.0 + device pci 1c.7 on end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x6f + irq 0xe1 = 0x1f + end + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x72 + irq 0xea = 0x00 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x0f + irq 0xf1 = 0x08 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0x9d + end + device pnp 2e.a on # ACPI + # Power RAM in S3 and let the PCH + # handle power failure actions + #irq 0xe4 = 0x70 + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z97_extreme6/dsdt.asl b/src/mainboard/asrock/z97_extreme6/dsdt.asl new file mode 100644 index 0000000..17c44b6 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads new file mode 100644 index 0000000..8c011b7 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this, there's DP, HDMI and DVI-I + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z97_extreme6/gpio.c b/src/mainboard/asrock/z97_extreme6/gpio.c new file mode 100644 index 0000000..1dee18c --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c new file mode 100644 index 0000000..dd31338 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862808, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x80860101), + AZALIA_PIN_CFG(0, 0x05, 0x18560010), + AZALIA_PIN_CFG(0, 0x06, 0x18560010), + AZALIA_PIN_CFG(0, 0x07, 0x18560010), + + /* TODO: Where did the codec on the PCH's HD Audio controller go? */ +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c new file mode 100644 index 0000000..6524077 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};
-
Angel Pons (Code Review)