Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30706
Change subject: mb/ocp/wedge100s: Disable internal uart ......................................................................
mb/ocp/wedge100s: Disable internal uart
Fix romstage serial console by disabling internal uart default setting. That redirects the uart to the LPC ITE superio.
Tested on wedge100s.
Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/wedge100s/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30706/1
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 5d4349d..18251c9 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -37,7 +37,7 @@ default 0x1000000
config DRIVERS_UART_8250IO - def_bool n + def_bool y
config FSP_PACKAGE_DEFAULT bool "Configure defaults for the Intel FSP package" @@ -47,4 +47,7 @@ string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+config INTEGRATED_UART + def_bool n + endif # BOARD_OCP_WEDGE100S
Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30706 )
Change subject: soc/intel/fsp_broadwell_de: Fix uart ......................................................................
soc/intel/fsp_broadwell_de: Fix uart
* Disable FSP serial output if not CONSOLE_SERIAL
Tested on wedge100s.
Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/30706 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 800f686..b64efce 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -66,6 +66,9 @@ UpdData->SerialPortBaudRate = 12; }
+ if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + UpdData->SerialPortType = 0; + /* * Memory Down */
-
Patrick Rudolph (Code Review)