Change in coreboot[master]: soc/intel/jasperlake: Update C-States info

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40902 )

Change subject: soc/intel/jasperlake: Update C-States info
......................................................................

soc/intel/jasperlake: Update C-States info

- Update C-States max latency values
- Remove MSR programming for C-States latency

BRANCH=None
TEST=Boot to OS and check CState Latenecy
> cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}

POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048

Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449
Signed-off-by: Ronak Kanabar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902
Reviewed-by: Aamir Bohra 
Reviewed-by: Maulik V Vaghela 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/jasperlake/acpi.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/jasperlake/include/soc/cpu.h
3 files changed, 20 insertions(+), 56 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aamir Bohra: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 373f95c..88ec5fe 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -52,70 +52,70 @@
 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
    [C_STATE_C0] = {},
    [C_STATE_C1] = {
-		.latency = 0,
+		.latency = C1_LATENCY,
    	.power = C1_POWER,
    	.resource = MWAIT_RES(0, 0),
    },
    [C_STATE_C1E] = {
-		.latency = 0,
+		.latency = C1_LATENCY,
    	.power = C1_POWER,
    	.resource = MWAIT_RES(0, 1),
    },
    [C_STATE_C6_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C6_LATENCY,
    	.power = C6_POWER,
    	.resource = MWAIT_RES(2, 0),
    },
    [C_STATE_C6_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C6_LATENCY,
    	.power = C6_POWER,
    	.resource = MWAIT_RES(2, 1),
    },
    [C_STATE_C7_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
    	.power = C7_POWER,
    	.resource = MWAIT_RES(3, 0),
    },
    [C_STATE_C7_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
    	.power = C7_POWER,
    	.resource = MWAIT_RES(3, 1),
    },
    [C_STATE_C7S_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
    	.power = C7_POWER,
    	.resource = MWAIT_RES(3, 2),
    },
    [C_STATE_C7S_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
    	.power = C7_POWER,
    	.resource = MWAIT_RES(3, 3),
    },
    [C_STATE_C8] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C8_LATENCY,
    	.power = C8_POWER,
    	.resource = MWAIT_RES(4, 0),
    },
    [C_STATE_C9] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C9_LATENCY,
    	.power = C9_POWER,
    	.resource = MWAIT_RES(5, 0),
    },
    [C_STATE_C10] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C10_LATENCY,
    	.power = C10_POWER,
    	.resource = MWAIT_RES(6, 0),
    },
 };

static int cstate_set_non_s0ix[] = {
-	C_STATE_C1E,
+	C_STATE_C1,
    C_STATE_C6_LONG_LAT,
    C_STATE_C7S_LONG_LAT
 };

static int cstate_set_s0ix[] = {
-	C_STATE_C1E,
+	C_STATE_C1,
    C_STATE_C7S_LONG_LAT,
    C_STATE_C10
 };
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 2533fe0..0c84468 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -137,39 +137,6 @@
    wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 }

-static void configure_c_states(void)
-{
-	msr_t msr;
-
-	/* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
-	msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
-	wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
-
-	/* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
-	msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
-	wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
-
-	/* C-state Interrupt Response Latency Control 3 - package C8 */
-	msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_32768_NS |
-		C_STATE_LATENCY_CONTROL_3_LIMIT;
-	wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
-
-	/* C-state Interrupt Response Latency Control 4 - package C9 */
-	msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_32768_NS |
-		C_STATE_LATENCY_CONTROL_4_LIMIT;
-	wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
-
-	/* C-state Interrupt Response Latency Control 5 - package C10 */
-	msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_32768_NS |
-		C_STATE_LATENCY_CONTROL_5_LIMIT;
-	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
-}
-
 /* All CPUs including BSP will run the following function. */
 void soc_core_init(struct device *cpu)
 {
@@ -183,9 +150,6 @@
    enable_lapic_tpr();
    setup_lapic();

-	/* Configure c-state interrupt response time */
-	configure_c_states();
-
    /* Configure Enhanced SpeedStep and Thermal Sensors */
    configure_misc();

diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h
index 1e5332d..c61f2ee 100644
--- a/src/soc/intel/jasperlake/include/soc/cpu.h
+++ b/src/soc/intel/jasperlake/include/soc/cpu.h
@@ -5,13 +5,13 @@

#include <intelblocks/msr.h>

-/* Latency times in units of 32768ns */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_1_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_2_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_3_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_4_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_5_LIMIT	0x9d
+/* Latency times in us */
+#define C1_LATENCY	1
+#define C6_LATENCY	127
+#define C7_LATENCY	253
+#define C8_LATENCY	260
+#define C9_LATENCY	487
+#define C10_LATENCY	1048

/* Power in units of mW */
 #define C1_POWER	0x3e8