Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15871
-gerrit
commit 90c8cc9b29956ac671aa1fd1895d0f2a0d294a6f Author: Jagadish Krishnamoorthy jagadish.krishnamoorthy@intel.com Date: Mon Jul 25 13:59:44 2016 -0700
soc/intel/apollolake: Configure gpio ownership
For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership.
BUG=chrome-os-partner:54371 TEST=none
Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy jagadish.krishnamoorthy@intel.com --- src/soc/intel/apollolake/gpio.c | 16 +++++++++++++++- src/soc/intel/apollolake/include/soc/gpio.h | 8 ++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 11 +++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index a3ffb3d..9da5ba3 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -86,11 +86,25 @@ static void gpio_configure_itss(const struct pad_config *cfg, void gpio_configure_pad(const struct pad_config *cfg) { const struct pad_community *comm = gpio_get_community(cfg->pad); - uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); + uint16_t pin = cfg->pad - comm->first_pad; + uint16_t config_offset = PAD_CFG_OFFSET(pin); + uint16_t hostsw_reg; + iosf_write(comm->port, config_offset, cfg->config0); iosf_write(comm->port, config_offset + sizeof(uint32_t), cfg->config1);
gpio_configure_itss(cfg, comm->port, config_offset); + /* Use the RO bit in pad_config 1 register to indicate the ownership */ + if (cfg->config1 & PAD_CFG1_GPIO_DRIVER) { + /* Based on the gpio pin number configure the + * corresponding bit in HOSTSW_OWN register. + * Value of 0x1 indicates Gpio Driver onwership. + */ + hostsw_reg = HOSTSW_OWN_REG_BASE + + ((pin / 32) * sizeof(uint32_t)); + iosf_write(comm->port, hostsw_reg, + iosf_read(comm->port, hostsw_reg) | 1 << (pin % 32)); + } }
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 1ebac2d..ec28e6e 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -56,6 +56,14 @@ typedef uint32_t gpio_t; PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull))
+/* General purpose input. The following macro sets the + * Host Software Pad Ownership to GPIO Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER) + /* No Connect configuration for unused pad. * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..4c6f62c 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -45,6 +45,12 @@ #define MISCCFG_GPE0_DW2_SHIFT 16 #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+/* Host Software Pad Ownership Register. + * The pins in the community are divided into 3 groups : + * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95 + */ +#define HOSTSW_OWN_REG_BASE 0x80 + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) @@ -75,6 +81,11 @@ #define PAD_CFG0_RESET_PLTRST (2 << 30) #define PAD_CFG0_RESET_RSMRST (3 << 30)
+/* Use the first bit in IntSel field to indicate gpio + * ownership. This field is RO and hence not used during + * gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 0) #define PAD_CFG1_IRQ_MASK (0xff << 0) #define PAD_CFG1_PULL_MASK (0xf << 10) #define PAD_CFG1_PULL_NONE (0x0 << 10)
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Jagadish Krishnamoorthy