[M] Change in coreboot[main]: soc/common/smbus: Support reading SPD5 hubs for DDR5

[Tim Crawford (Code Review)]

Attention is currently required from: Angel Pons, Balaji Manigandan, Balaji Manigandan, Eric Lai, Haribalaraman Ramasubramanian, Jeremy Soller, Kapil Porwal, Karthik Ramasubramanian, Kyösti Mälkki, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Paul Menzel, Raj Astekar, Reka Norman, Rizwan Qureshi, Subrata Banik, Subrata Banik, Tarun Tuli, Tim Wawrzynczak.

Tim Crawford has posted comments on this change by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email )

Change subject: soc/common/smbus: Support reading SPD5 hubs for DDR5
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Patch Set 16:

(9 comments)

Patchset:

PS13:
> Yes. We have cherry-picked this in order to remove the workaround in `meminit. […]
> Done

Patchset:

PS14:
> Adding Intel team to take care of this CL
> Taking over since no one from Intel responded.

PS14:
> @Meera, any plan to address this ?
> Guess not.

Patchset:

PS16: 
Intel has seemingly abandoned this work, so I've updated with the changes Jeremy has made while working on the Clevo RPL and MTL units.

I've moved Meera to co-author for the original work and made Jeremy the commit author, as he has rewritten it as part of the work for adding support for Clevo L240TU (system76/lemp13).


Commit Message:

https://review.coreboot.org/c/coreboot/+/52731/comment/3b40b37b_1b66f3d8?usp... :
PS13, Line 7: Add support for reading spd data via smbus for DDR5
> “Add support for” can be substituted by “Support”: […]
> Done

https://review.coreboot.org/c/coreboot/+/52731/comment/f3abba1b_dd72dcc9?usp... :
PS13, Line 11: This CL adds support to read the spd5 hub device via smbus.
> Please add a blank line above to separate the paragraphs.
> Acknowledged

https://review.coreboot.org/c/coreboot/+/52731/comment/d12a4efb_fa2422d5?usp... :
PS13, Line 14: TEST=Boot adlrvp DDR5 board to kernel
> Before it didn’t work? What RAM modules did you test with?
> Acknowledged

File src/soc/intel/common/block/smbus/smbuslib.c:

https://review.coreboot.org/c/coreboot/+/52731/comment/7902c4e7_d4e6cd1a?usp... :
PS13, Line 10: {   0,               1 }, /* General Configuration section */
             : {   2,               2 }, /* General Configuration section */
             : {   3,              47 }, /* General Configuration section */
> I see, it's inclusive. So yes, they are contiguous. Probably just copied from the FSP then. […]
> Removed

https://review.coreboot.org/c/coreboot/+/52731/comment/159a2814_4b203d03?usp... :
PS13, Line 54: /*
             : 	*  By default,an SPD5 hub accepts 1 byte addressing pointing
             : 	*  to the first 128 bytes of memory. MR11[2:0] selects the page
             : 	*  pointer to address the entire 1024 bytes of non-volatile memory.
             : 	*/
> Please use one of the recommended multi-line comment styles.
> Done