Patch set updated for coreboot: fba9056 exynos5420: Set SPLL to 400MHz

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4464

-gerrit

commit fba9056560c2024f8c758cc2371144a2d10f780b
Author: David Hendricks 
Date:   Fri Aug 9 18:59:02 2013 -0700

exynos5420: Set SPLL to 400MHz

Increase SPLL to 400MHz from 300MHz as we set SPLL as the
    switching parent for ARM and KFC. This value is as per
    recommendation of the hardware team.

This is ported from https://gerrit.chromium.org/gerrit/62618

Signed-off-by: David Hendricks

Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223
    Reviewed-on: https://gerrit.chromium.org/gerrit/65432
    Reviewed-by: Gabe Black 
    Tested-by: David Hendricks 
    Commit-Queue: Gabe Black 
---
 src/cpu/samsung/exynos5420/clock_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c
index 07bf5d9..8be286d 100644
--- a/src/cpu/samsung/exynos5420/clock_init.c
+++ b/src/cpu/samsung/exynos5420/clock_init.c
@@ -141,7 +141,7 @@ void system_clock_init(void)

/* Set SPLL */
    writel(SPLL_CON1_VAL, &clk->spll_con1);
-	val = set_pll(0xc8, 0x2, 0x3);
+	val = set_pll(200, 0x3, 0x2);	/* 400MHz */
    writel(val, &clk->spll_con0);
    while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
    	;