Patch merged into coreboot/master: 21c908b exynos5420: re-factor clock_get_periph_rate()

the following patch was just integrated into master:
commit 21c908bf6280b4c52dc983f0deb25b3439f75b27
Author: David Hendricks 
Date:   Thu Aug 8 20:45:53 2013 -0700

exynos5420: re-factor clock_get_periph_rate()

This re-factors clock_get_periph_rate() to be a simpler and also
    make a few corrections along the way. To summarize:

- clk_bit_info is no longer used. It had numerous errors and was
      really painful anyway since it was just a bunch of opaque magic
      numbers that made bugs non-obvious.

- Clock source bitfields for peripherals handled in the switch
      statement are 3 bits, not 4. Some divider values are 3 bits,
      some are 4. The earlier code always assumed 4 bits for both
      which included reserved bits in many cases.

- UART source clock and divider shift values were wrong.

- PWM clock divider was being read from the wrong register.

- SPI3 divider value was being read from the wrong register.

- There was a really confusing calculation for SDMMC0 and SDMMC2
      clock rates, but it was never actually used since the switch
      statement never handled PERIPH_ID_SDMMC{0,2} and would thus
      return if they were ever passed into this function.

Signed-off-by: David Hendricks

Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b
    Reviewed-on: https://gerrit.chromium.org/gerrit/65284
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    Reviewed-by: Gabe Black

See http://review.coreboot.org/4463 for details.

-gerrit