Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, V Sowmya, Vinay Kumar.
Vidya Gopalakrishnan has posted comments on this change by Vidya Gopalakrishnan. ( https://review.coreboot.org/c/coreboot/+/85184?usp=email )
Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W ......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85184/comment/4388058d_0b0f8abe?usp... : PS4, Line 7: Update
Decrease
The PL1 values are already set elsewhere in code based on silicon ID. In this patch I am only removing the PL1 override to a higher value. Hence reworded to "Remove overriding of PL1 value to 20W".
https://review.coreboot.org/c/coreboot/+/85184/comment/2485213c_43704e1c?usp... : PS4, Line 9: Update the RAPL PL1 limit and MMIO PL1 max values as per silicon TDP.
Please mention the values.
Done
https://review.coreboot.org/c/coreboot/+/85184/comment/22868d40_97a7cd5a?usp... : PS4, Line 13: Verified PL1 value is updated in DTT and sysfs interfaces.
Please paste the commands and the output.
Done
File src/mainboard/google/brya/variants/trulo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85184/comment/41c545fb_23942215?usp... : PS4, Line 184: register "power_limits_config[ADL_N_041_6W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 25, : .tdp_pl4 = 78, : }" : : register "power_limits_config[ADL_N_081_7W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 25, : .tdp_pl4 = 78, : }" : : register "power_limits_config[ADL_N_081_15W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 35, : .tdp_pl4 = 83, : }"
wondering if your goal is to block PLx overrides which I felt is something that many ODMs are using […]
PL1/PL2 override hooks can still be used by ODMs by adding this block of code back. But overriding PL1/PL2 to a higher value as done here should not be a default guidance given from a reference design as using a higher PLx can have thermal impacts to silicon. This code block seems to be copied from some other production device variant that is also using a higher override for PLx values. Such overrides are not part of any other reference design variant.