[S] Change in coreboot[main]: intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81314?usp=email )

(

25 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
......................................................................

intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE

IBL (Integrated Boot Logic) provides a subset of server
PCH logics for no-PCH solution. IBL is with limited features
and registers exposed, PCIe root ports/USB/SATA/LAN support are
removed.

Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259
Signed-off-by: Shuo Liu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/pch/Kconfig
M src/soc/intel/common/pch/Makefile.mk
M src/soc/intel/xeon_sp/Kconfig
3 files changed, 44 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved

diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index 716a786..32902aa 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -75,3 +75,36 @@
    select SOC_INTEL_COMMON_BLOCK_XDCI

endif # SOC_INTEL_COMMON_PCH_BASE
+
+config SOC_INTEL_COMMON_IBL_BASE
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK
+	depends on !SOC_INTEL_COMMON_PCH_BASE
+	help
+	  Common code blocks for integrated boot logic known as IBL. IBL is still
+	  compatible with PCH interfaces, but with limited features/registers
+	  exposed and certain revises.
+
+if SOC_INTEL_COMMON_IBL_BASE
+
+source "src/soc/intel/common/pch/*/Kconfig"
+
+config IBL_SPECIFIC_BASE_OPTIONS
+	def_bool y
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
+	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+	select SOC_INTEL_COMMON_BLOCK_GPIO
+	select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
+	select SOC_INTEL_COMMON_BLOCK_ITSS
+	select SOC_INTEL_COMMON_BLOCK_LPC
+	select SOC_INTEL_COMMON_BLOCK_P2SB
+	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_PMC
+	select SOC_INTEL_COMMON_BLOCK_RTC
+	select SOC_INTEL_COMMON_BLOCK_SMBUS
+	select SOC_INTEL_COMMON_BLOCK_SPI
+	select SOC_INTEL_COMMON_BLOCK_TIMER
+	select SOC_INTEL_COMMON_PCH_LOCKDOWN
+	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+
+endif # SOC_INTEL_COMMON_IBL_BASE
diff --git a/src/soc/intel/common/pch/Makefile.mk b/src/soc/intel/common/pch/Makefile.mk
index 19c17d5..ef9044b 100644
--- a/src/soc/intel/common/pch/Makefile.mk
+++ b/src/soc/intel/common/pch/Makefile.mk
@@ -1,6 +1,11 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 subdirs-$(CONFIG_SOC_INTEL_COMMON_PCH_BASE) += ./*
+subdirs-$(CONFIG_SOC_INTEL_COMMON_IBL_BASE) += ./*

ifeq ($(CONFIG_SOC_INTEL_COMMON_PCH_BASE),y)
 CPPFLAGS_common += -I$(src)/soc/intel/common/pch/include/
 endif
+
+ifeq ($(CONFIG_SOC_INTEL_COMMON_IBL_BASE),y)
+CPPFLAGS_common += -I$(src)/soc/intel/common/pch/include/
+endif
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 923527e3..78227ed 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -2,6 +2,10 @@

source "src/soc/intel/xeon_sp/*/Kconfig"

+config XEON_SP_IBL
+	bool
+	default n
+
 config XEON_SP_COMMON_BASE
    bool
    select ACPI_INTEL_HARDWARE_SLEEP_VALUES
@@ -31,9 +35,10 @@
    select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_TCO
-	select SOC_INTEL_COMMON_PCH_SERVER
    select SUPPORT_CPU_UCODE_IN_CBFS
    select SMM_PCI_RESOURCE_STORE
+	select SOC_INTEL_COMMON_PCH_SERVER if !XEON_SP_IBL
+	select SOC_INTEL_COMMON_IBL_BASE if XEON_SP_IBL
    select TSC_MONOTONIC_TIMER
    select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT
    select UDELAY_TSC