Change in coreboot[master]: md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M
......................................................................

md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M

As with the FSP-M for Intel Skylake-SP [1], we should be sure that
after romstage the pads will be configured according to the config
from gpio.h only. This patch sets the GPIO configuration from gpio.h
using the soc/intel/common/gpio.c driver again in ramstage.

[1]

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40735/1

diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
new file mode 100644
index 0000000..f4c716e
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* configure Lewisburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M
......................................................................

md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M

As with the FSP-M for Intel Skylake-SP [1], we should be sure that
after romstage the pads will be configured according to the config
from gpio.h only. This patch sets the GPIO configuration from gpio.h
using the soc/intel/common/gpio.c driver again in ramstage.

[1]

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40735/2

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40735

to look at the new patch set (#4).

Change subject: md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M
......................................................................

md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M

As with the FSP-M for Intel Skylake-SP [1], we should be sure that
after romstage the pads will be configured according to the config
from gpio.h only. This patch sets the GPIO configuration from gpio.h
using the soc/intel/common/gpio.c driver again in ramstage.

[1] https://review.coreboot.org/c/coreboot/+/40730

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40735/4

Change in coreboot[master]: md/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40735

to look at the new patch set (#5).

Change subject: md/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

md/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

We should be sure that after romstage the pads will be configured
according to the config from gpio.h only. This patch sets the GPIO
configuration from gpio.h using the soc/intel/common/gpio.c driver
again in ramstage.

[1] https://review.coreboot.org/c/coreboot/+/40730

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40735/5

Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40735

to look at the new patch set (#7).

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

We should be sure that after romstage the pads will be configured
according to the config from gpio.h only. This patch sets the GPIO
configuration from gpio.h using the soc/intel/common/gpio.c driver
again in ramstage.

[1] https://review.coreboot.org/c/coreboot/+/40730

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40735/7

Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[Andrey Petrov (Code Review)]

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

We should be sure that after romstage the pads will be configured
according to the config from gpio.h only. This patch sets the GPIO
configuration from gpio.h using the soc/intel/common/gpio.c driver
again in ramstage.

[1] https://review.coreboot.org/c/coreboot/+/40730

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735
Tested-by: build bot (Jenkins) 
Reviewed-by: Andrey Petrov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Andrey Petrov: Looks good to me, approved

diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
new file mode 100644
index 0000000..f4c716e
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* configure Lewisburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

Patch Set 8:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2964
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2963
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2962
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2961

Please note: This test is under development and might not be accurate at all!

Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

Patch Set 8:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2970
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2969
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2968
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2967

Please note: This test is under development and might not be accurate at all!

Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
......................................................................

Patch Set 8:

this could never work because ramstage.c is not handled by default. For some reason this even seems to be somehow broken. I didn't find the problem, yet. See CB:41106