Patch merged into coreboot/master: soc/intel/skylake: indicate voltage margining enabled/disabled

the following patch was just integrated into master:
commit 0da186c3ffb1d9aa7433a5d0d5263aba7a25ad60
Author: Rizwan Qureshi 
Date:   Thu Feb 23 14:43:39 2017 +0530

soc/intel/skylake: indicate voltage margining enabled/disabled

Support for voltage margining is dependent on the platform.
    Enabling voltage margining puts additional constraints for
    the SLP_S0# to be asserted and hence moving to S0ix state.
    If the platform PMIC/VR supports PCH voltage reduction,
    voltage marigining can be enabled.

Use the UPD provided by FSP to enable/disable voltage margining.

Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
    Signed-off-by: Rizwan Qureshi 
    Reviewed-on: https://review.coreboot.org/18469
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel 
    Reviewed-by: Aaron Durbin

See https://review.coreboot.org/18469 for details.

-gerrit