Change in coreboot[master]: soc/intel/*: only enable PM Timer emulation if the PM Timer is disabled

[Michael Niewöhner (Code Review)]

Attention is currently required from:  Felix Singer, Lance Zhao, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Aaron Durbin, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57930 )

Change subject: soc/intel/*: only enable PM Timer emulation if the PM Timer is disabled
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Patch Set 4:

(1 comment)

Patchset:

PS4:
> > I wonder why the SKL/KBL BIOS spec says that ACPI timer emulation should always be enabled.  […]

Reading SKL/KBL BWG once again, I realized that it mentions idle states. I have some idea..... could it be that microcode does not *always* redirect read/writes to/from the timer but *only* when it's disabled??

"Some legacy OSes cannot tolerate ACPI timer stop running during idle states,
therefore, result in more power consumption. Intel microarchitecture code name
Skylake and Kaby Lake support ACPI Timer Emulation via MSR 0x121.

The emulated ACPI timer allows disabling of the ACPI Timer (PM1_TMR) to have no
impact on the system, with the exception that TMR_STS will not be set on an overflow condition. All aligned 32-bit reads to the ACPI Timer port are valid and will behave as if the ACPI timer remains enabled."