Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30272 )
Change subject: nb/intel/haswell: Add support for PCIe graphics ......................................................................
Patch Set 7:
(1 comment)
I've repeated the tests on the latest patch set.
https://review.coreboot.org/#/c/30272/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30272/6//COMMIT_MSG@11 PS6, Line 11: class present in a PEG slot, disable the IGD: : : Before the MRC: GGC = 0x0208, DEVEN = 0x00000039. : After the MRC: GGC = 0x0003, DEVEN = 0x00000029. : : If the IGD needs to be kept enabled, the PEG device is hidden while the : MRC runs. The link training is able to continue even while the PEG : device is hidden. : : Only PEG2 is supported. An extra (unknown) training sequence is said to : be needed for PEG3. : : The ACPI _PRT method is not yet generated, so legacy interrupt routing : doesn't work for devices with multiple functions. : : Tested on an ASRock H81M-HDS. Using an x1 PCIe card in the PEG slot : works fine. Using a Rade
Would the following work? […]
Thank you for this idea! It looks like the link training continues even when the PEG device is disabled. I've updated the patch to use this approach, so there is now only a single boot flow.
-
Tristan Corrick (Code Review)