New patch to review for coreboot: imgtec/pistachio: DDR2, DDR3: DLL reset set

[Ionela Voinescu]

Ionela Voinescu ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12764

-gerrit

commit bfc9c63b79647814ae92982b1224e322705ae6c9
Author: Ionela Voinescu 
Date:   Tue May 26 12:20:19 2015 +0100

imgtec/pistachio: DDR2, DDR3: DLL reset set

Bit 8 of the MR register is automatically set by the PHY
    during memory initilization but having it set in the
    register leads to a more clear understanding.

Tested on Pistachio bring up board; DDR2 and DDR3 are
    initialized properly.

Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
    Signed-off-by: Ionela Voinescu 
---
 src/soc/imgtec/pistachio/ddr2_init.c | 2 +-
 src/soc/imgtec/pistachio/ddr3_init.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index 322d241..9549537 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -112,7 +112,7 @@ int init_ddr2(void)
     * 15:13 RSVD RSVD
     * 31:16 Reserved
     */
-	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000A62 | (BL8 ? 0x1 : 0x0));
+	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0));
    /* MR1 : EMR Register
     * Generate to use with PHY and PCTL
     * 0 DE DLL Enable 0 Disable 1
diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c
index e77a5cd..5cb36a0 100644
--- a/src/soc/imgtec/pistachio/ddr3_init.c
+++ b/src/soc/imgtec/pistachio/ddr3_init.c
@@ -119,7 +119,7 @@ int init_ddr3(void)
     * 15:13 RSVD RSVD
     * 31:16 Reserved
     */
-	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001420);
+	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
    /* MR1 : DDR3 mode register 1
     * Generate to use with PHY and PCTL
     * 0 DE DLL Enable 0 Disable 1