Change in coreboot[master]: soc/alderlake: Fix DDR5 boot hang due to incorrect array size

[Angel Pons (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Ronak Kanabar, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 )

Change subject: soc/alderlake: Fix DDR5 boot hang due to incorrect array size
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Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/52730/comment/6b1e7146_5c99da2b 
PS1, Line 10: of MRC channels.
Why? `struct spd_block` is independent of the interface used by MRC/FSP.

File src/include/spd_bin.h:

https://review.coreboot.org/c/coreboot/+/52730/comment/0b7f6f06_59f43f04 
PS1, Line 8: #include <soc/meminit.h>
Uh, this is backwards. Common code shouldn't depend on SoC-specific headers.