the following patch was just integrated into master: commit d8a5017ee0d47e860148d139bc5329083ac06515 Author: Joseph Lo josephl@nvidia.com Date: Fri Apr 17 15:31:59 2015 +0800
arm64: save/restore cptr_el3 and cpacr_el1 registers
CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level and access right of the FPU/SIMD instructions. Need to save/restore them in every power cycle to keep the settings consistent.
BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well
Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057 Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd Original-Signed-off-by: Joseph Lo josephl@nvidia.com Original-Reviewed-on: https://chromium-review.googlesource.com/266073 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-by: Benson Leung bleung@chromium.org Reviewed-on: http://review.coreboot.org/9981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones marc.jones@se-eng.com
See http://review.coreboot.org/9981 for details.
-gerrit