Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS grap...

[Abhay Kumar (Code Review)]

Abhay Kumar has uploaded this change for review. ( https://review.coreboot.org/22799

Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics.
......................................................................

soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics.

TEST=Edp should come up in normal mode.

Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef
Signed-off-by: Abhay Kumar 
---
M src/soc/intel/cannonlake/graphics.c
1 file changed, 37 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/22799/1

diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
index 5cf0ec8..6e1142a 100644
--- a/src/soc/intel/cannonlake/graphics.c
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -21,12 +21,49 @@
 #include <device/pci.h>
 #include <drivers/intel/gma/opregion.h>
 #include <intelblocks/graphics.h>
+#include <drivers/intel/gma/i915_reg.h>

uintptr_t fsp_soc_get_igd_bar(void)
 {
    return graphics_get_memory_base();
 }

+void graphics_soc_init(struct device *dev)
+{
+	u32 ddi_buf_ctl;
+
+	/*
+	* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
+	* This will allow the kernel to use 4-lane eDP links properly
+	* if the VBIOS or GOP driver does not execute.
+	*/
+	ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
+	if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
+		ddi_buf_ctl |= DDI_A_4_LANES;
+		graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
+	}
+
+	/*
+	* GFX PEIM module inside FSP binary is taking care of graphics
+	* initialization based on INTEL_GMA_ADD_VBT_DATA_FILE Kconfig
+	* option and input VBT file. Hence no need to load/execute legacy VGA
+	* OpROM in order to initialize GFX.
+	*
+	* In case of non-FSP solution, SoC need to select VGA_ROM_RUN
+	* Kconfig to perform GFX initialization through VGA OpRom.
+	*/
+	if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))
+		return;
+
+	/* IGD needs to Bus Master */
+	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Initialize PCI device, load/execute BIOS Option ROM */
+	pci_dev_init(dev);
+}
+
 uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
    	uintptr_t current, struct acpi_rsdp *rsdp)
 {