Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size a devicetree parameter

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856

-gerrit

commit 4a9da310e35723058a49ca9f7dce5b16d10ae8db
Author: Arthur Heymans 
Date:   Mon Oct 3 17:16:48 2016 +0200

nb/intel/i945: make pci_mmio_size a devicetree parameter

Instead of hardcoding pci_mmio_size in the raminit code,
    this makes it a parameter in the devicetree.

Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
    Signed-off-by: Arthur Heymans 
---
 src/mainboard/apple/macbook21/devicetree.cb |  2 ++
 src/mainboard/lenovo/t60/devicetree.cb      |  2 ++
 src/mainboard/lenovo/x60/devicetree.cb      |  2 ++
 src/northbridge/intel/i945/chip.h           |  1 +
 src/northbridge/intel/i945/raminit.c        | 21 ++++++++++++++++++---
 5 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index 4bbe28d..f37e768 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -30,6 +30,8 @@ chip northbridge/intel/i945
    	end
    end

+	register "pci_mmio_size" = "768"
+
    device domain 0 on
    	device pci 00.0 on # Host bridge
    		subsystemid 0x8086 0x7270
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 2dc9f45..f66455b 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -30,6 +30,8 @@ chip northbridge/intel/i945
    	end
    end

+	register "pci_mmio_size" = "768"
+
    device domain 0 on
    	device pci 00.0 on # Host bridge
    		subsystemid 0x17aa 0x2015
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index e2a24c1..0ac9273 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -30,6 +30,8 @@ chip northbridge/intel/i945
    	end
    end

+	register "pci_mmio_size" = "768"
+
    device domain 0 on
    	device pci 00.0 on # Host bridge
    		subsystemid 0x17aa 0x2017
diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h
index 446af72..c6d80e6 100644
--- a/src/northbridge/intel/i945/chip.h
+++ b/src/northbridge/intel/i945/chip.h
@@ -8,6 +8,7 @@ struct northbridge_intel_i945_config {
    u32 gpu_backlight;
    int gpu_lvds_use_spread_spectrum_clock;
    struct i915_gpu_controller_info gfx;
+	u16 pci_mmio_size;
 };

#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 0b9e95c..fa70a76 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -16,6 +16,8 @@
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <device/pci_def.h>
+#include <device/device.h>
 #include <lib.h>
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
@@ -25,6 +27,7 @@
 #include <lib.h>
 #include "raminit.h"
 #include "i945.h"
+#include "chip.h"
 #include <cbmem.h>

/* Debugging macros. */
@@ -48,6 +51,7 @@
 #define RAM_EMRS_2			(0x1 << 21)
 #define RAM_EMRS_3			(0x2 << 21)

+#define DEFAULT_PCI_MMIO_SIZE		768
 static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
 {
    if (sysinfo->spd_addresses)
@@ -1503,7 +1507,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 {
    int i;
-	int cum0, cum1, tolud, tom;
+	int cum0, cum1, tolud, tom, pci_mmio_size;
+	const struct device *dev;
+	const struct northbridge_intel_i945_config *cfg = NULL;

printk(BIOS_DEBUG, "Setting RAM size...\n");

@@ -1542,8 +1548,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
    tom = tolud >> 3;

/* Limit the value of TOLUD to leave some space for PCI memory. */
-	if (tolud > 0xd0)
-		tolud = 0xd0;	/* 3.25GB : 0.75GB */
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (dev)
+		cfg = dev->chip_info;
+
+	/* If this is zero, it just means devicetree.cb didn't set it */
+	if (!cfg || cfg->pci_mmio_size == 0)
+		pci_mmio_size = DEFAULT_PCI_MMIO_SIZE;
+	else
+		pci_mmio_size = cfg->pci_mmio_size;
+
+	tolud = MIN((ALIGN_DOWN(4096 - pci_mmio_size, 128) / 128) << 3, tolud);

pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);