New patch to review for coreboot: 624f9af nyan: Initialize the i2c pins and controllers.

[Isaac Christensen]

Isaac Christensen ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6866

-gerrit

commit 624f9af237d3ce601c8fb81eac3d95f73718ec15
Author: Gabe Black 
Date:   Thu Oct 10 03:46:14 2013 -0700

nyan: Initialize the i2c pins and controllers.

Set up the i2c controllers that are used on nyan.

Old-Change-Id: Ibdd5685e3effdd13ca560b8f18db25e9edadc07b
    Signed-off-by: Gabe Black 
    Reviewed-on: https://chromium-review.googlesource.com/172584
    Reviewed-by: Ronald Minnich 
    Reviewed-by: Julius Werner 
    Tested-by: Gabe Black 
    Commit-Queue: Gabe Black 
    (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8)

nyan: Initialize the PMIC.

Add code which initializes the AS3722 PMIC based on the initialization
    sequence U-Boot uses. I wasn't able to find documentation which said what each
    register in the PMIC does, so the next best solution was to imitate another
    implementation which presumably sets things up correctly.

The code is set up significantly differently than the U-Boot code, first
    because it uses the i2c driver through it's external interface instead of
    poking values into the controller's registers directly. The driver uses the
    packet mode of the controller while the U-Boot code does not. Second, it uses
    an array of register indices and values, a pattern established with Exynos,
    instead of having a sequence of calls to the i2c_write function.

This change is also a practical test of the i2c driver's write capability.

Old-Change-Id: Iab1f8d3b735b0737ce93ee3c9c7fdb2a1dcbbf8a
    Signed-off-by: Gabe Black 
    Reviewed-on: https://chromium-review.googlesource.com/172585
    Reviewed-by: Ronald Minnich 
    Reviewed-by: Julius Werner 
    Tested-by: Gabe Black 
    Commit-Queue: Gabe Black 
    (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a)

Squashed nyan i2c related commits.

Change-Id: I04d7f770ed2ff62d43da637671d2f58d5c340fd6
    Signed-off-by: Isaac Christensen 
---
 src/mainboard/google/nyan/Makefile.inc |  1 +
 src/mainboard/google/nyan/bootblock.c  | 38 +++++++++++++++++
 src/mainboard/google/nyan/pmic.c       | 78 ++++++++++++++++++++++++++++++++++
 src/mainboard/google/nyan/pmic.h       | 25 +++++++++++
 4 files changed, 142 insertions(+)

diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index 2dfd2a3..f154a3b 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -28,6 +28,7 @@ $(obj)/generated/bct.cfg:
 subdirs-y += bct

bootblock-y += bootblock.c
+bootblock-y += pmic.c

romstage-y += romstage.c

diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
index e193ab1..fe938b4 100644
--- a/src/mainboard/google/nyan/bootblock.c
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -18,9 +18,47 @@
  */

#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/clock.h>
+#include <soc/nvidia/tegra124/pinmux.h>
+
+#include "pmic.h"

void bootblock_mainboard_init(void)
 {
    clock_config();
+
+	// I2C1 clock.
+	pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
+			  PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+	// I2C1 data.
+	pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
+			  PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+	// I2C2 clock.
+	pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
+			  PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+	// I2C2 data.
+	pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
+			  PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+	// I2C3 (cam) clock.
+	pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+			  PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+	// I2C3 (cam) data.
+	pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+			  PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+	// I2C5 (PMU) clock.
+	pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
+			  PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+	// I2C5 (PMU) data.
+	pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
+			  PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+
+	i2c_init(0);
+	i2c_init(1);
+	i2c_init(2);
+	i2c_init(4);
+
+	pmic_init(4);
 }
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
new file mode 100644
index 0000000..ab951ea
--- /dev/null
+++ b/src/mainboard/google/nyan/pmic.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "pmic.h"
+
+struct pmic_write
+{
+	uint8_t reg; // Register to write.
+	uint8_t val; // Value to write.
+};
+
+enum {
+	AS3722_I2C_ADDR = 0x40
+};
+
+static struct pmic_write pmic_writes[] =
+{
+	/* Don't need to set up VDD_CORE - already done - by OTP */
+
+	/* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */
+	{ 0x00, 0x28 },
+
+	/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+
+	/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
+	{ 0x06, 0x28 },
+
+	/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+
+	/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
+	{ 0x12, 0x10 },
+
+	/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	{ 0x16, 0x3f }
+
+	/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+};
+
+void pmic_init(unsigned bus)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
+		i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1,
+			  &pmic_writes[i].val, 1);
+		udelay(10 * 1000);
+	}
+}
diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h
new file mode 100644
index 0000000..78c9f0d
--- /dev/null
+++ b/src/mainboard/google/nyan/pmic.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__
+#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */