Change in coreboot[master]: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41978 )
Change subject: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax ......................................................................
northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/link.
Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl 1 file changed, 26 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41978/1
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index c3561f8..c8efc98 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -130,17 +130,16 @@ External (_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (_SB.CP00._PSS)
- While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ }
Return (0) @@ -160,23 +159,23 @@ Store ("Set TDP Down", Debug)
/* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD
/* Set TAR */ - Store (TARD, TARS) + TARS = TARD
/* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN ()
/* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, , PL2V) + PL2V = (CTDD * 125) / 100
/* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD
/* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD
Release (CTCM) Return (1) @@ -196,23 +195,23 @@ Store ("Set TDP Nominal", Debug)
/* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN
/* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, , PL2V) + PL2V = (CTDN * 125) / 100
/* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN ()
/* Set TAR */ - Store (TARN, TARS) + TARS = TARN
/* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN
/* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN
Release (CTCM) Return (1) @@ -343,18 +342,18 @@
// Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) + Local0 = ^MCHC.TLUD + Local1 = ^MCHC.MEBA
// Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) + Local0 = ^MCHC.TOM }
- Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = Local0 + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = PMAX - PMIN + 1
Return (MCRS) }
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41978 )
Change subject: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41978 )
Change subject: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax ......................................................................
northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/link.
Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl 1 file changed, 26 insertions(+), 27 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index c3561f8..c8efc98 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -130,17 +130,16 @@ External (_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (_SB.CP00._PSS)
- While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ }
Return (0) @@ -160,23 +159,23 @@ Store ("Set TDP Down", Debug)
/* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD
/* Set TAR */ - Store (TARD, TARS) + TARS = TARD
/* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN ()
/* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, , PL2V) + PL2V = (CTDD * 125) / 100
/* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD
/* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD
Release (CTCM) Return (1) @@ -196,23 +195,23 @@ Store ("Set TDP Nominal", Debug)
/* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN
/* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, , PL2V) + PL2V = (CTDN * 125) / 100
/* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN ()
/* Set TAR */ - Store (TARN, TARS) + TARS = TARN
/* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN
/* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN
Release (CTCM) Return (1) @@ -343,18 +342,18 @@
// Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) + Local0 = ^MCHC.TLUD + Local1 = ^MCHC.MEBA
// Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) + Local0 = ^MCHC.TOM }
- Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = Local0 + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = PMAX - PMIN + 1
Return (MCRS) }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41978 )
Change subject: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4803 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4802 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4801 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4800
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)