Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22795
Change subject: [NOTFORMERGE] nb/sandybridge/raminit: print write training statistics ......................................................................
[NOTFORMERGE] nb/sandybridge/raminit: print write training statistics
for debug purposes...
Change-Id: I8033517f1bc877875ccd7ef950329b8b251fc2c2 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/22795/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index eaef5f7..64a4808 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1551,6 +1551,7 @@ int timC; int statistics[NUM_LANES][MAX_TIMC + 1]; int lane; + int i;
wait_428c(channel);
@@ -1577,6 +1578,13 @@ } } FOR_ALL_LANES { + printk(RAM_SPEW, "statistics lane %d:\n", lane); + for (i = 0; i < MAX_TIMC + 1; i++) { + printk(RAM_SPEW, " 0x%x", statistics[lane][i]); + if (!(i % 16)) + printk(RAM_SPEW, "\n"); + } + printk(RAM_SPEW, "\n"); struct run rn = get_longest_zero_run(statistics[lane], MAX_TIMC + 1); ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle;