Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F

[Michael Niewöhner (Code Review)]

Attention is currently required from: Christian Walter, Angel Pons, Arthur Heymans.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 )

Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
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Patch Set 72:

(1 comment)

File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md:

https://review.coreboot.org/c/coreboot/+/37441/comment/d6aa5a83_a652f46e 
PS64, Line 31: 0x235=03 and 0x13E=84
> I remember reading somewhere that these offsets seem to be wrong. I haven't checked them myself.

I have no access to the CNP SPI programming guide, however, building enabled/disabled images with FIT and comparing revealed these offsets:

- 0x234 : en/dis (0/1) <- latest image from Supermicro has this set already
            ^-- 4, not 5
- 0x13D : frequency, 0x06 = 17 MHz, 0x02 = 48 MHz
            ^-- D, not E

So.... where do your offset/value pairs come from?

Also, according to the product page, it's a Infineon 9670 TPM, which only supports a maximum of 48 MHz according to its datasheet. While 48 MHz might work on your specific TPM does not mean that it will work on anyone's.