the following patch was just integrated into master: commit 29dd5da1dc577bf97cb85998b17b2e163a5ab86e Author: Timothy Pearson firstname.lastname@example.org Date: Fri Apr 29 01:35:21 2016 -0500
nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
During DQS receiver enable cycle training on Family 15h platforms the read data timing registers were inadvertently set to zero on every lane training attempt.
Ensure that the read data timing registers are correctly set after each lane is trained in receiver enable cycle training. This allows more than one RDIMM to function on a given DCT channel.
Change-Id: I87d732f0383e9785a73b57e6f48855f3e872f1f9 Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262HE Tested-With: 4x Crucial 36KSF1G72PZ-1G6M1 (slots A2 / A1 / B2 / B1) Signed-off-by: Timothy Pearson email@example.com Reviewed-on: https://review.coreboot.org/14543 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand firstname.lastname@example.org Reviewed-by: Martin Roth email@example.com
See https://review.coreboot.org/14543 for details.