Change in coreboot[master]: Revert "mb/intel/shadowmountain: Add the ASL code"

[Patrick Georgi (Code Review)]

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra.
Hello V Sowmya, build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/50055

to review the following change.

Change subject: Revert "mb/intel/shadowmountain: Add the ASL code"
......................................................................

Revert "mb/intel/shadowmountain: Add the ASL code"

This reverts commit 2151f7561d728a9280d69d20ef56a9fe44db7cb1.

Reason for revert: It depends on one of the other shadowmountain patches, probably the ramstage code. Error on the builder:

IASL       /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml
src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory
 #include <baseboard/ec.h>
          ^~~~~~~~~~~~~~~~
compilation terminated.

Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab
---
M src/mainboard/intel/shadowmountain/dsdt.asl
1 file changed, 0 insertions(+), 29 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/50055/1

diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl
index f94ad37..c8dc9ee 100644
--- a/src/mainboard/intel/shadowmountain/dsdt.asl
+++ b/src/mainboard/intel/shadowmountain/dsdt.asl
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <acpi/acpi.h>
-#include <baseboard/ec.h>
-#include <baseboard/gpio.h>

DefinitionBlock(
    "dsdt.aml",
@@ -14,31 +12,4 @@
 )
 {
    #include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-
-	/* global NVS and variables */
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-
-	/* CPU */
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-			#include <soc/intel/alderlake/acpi/southbridge.asl>
-			#include <soc/intel/alderlake/acpi/tcss.asl>
-		}
-	}
-
-	/* Chrome OS Embedded Controller */
-	Scope (_SB.PCI0.LPCB)
-	{
-		// ACPI code for EC SuperIO functions
-		#include <ec/google/chromeec/acpi/superio.asl>
-		// ACPI code for EC functions
-		#include <ec/google/chromeec/acpi/ec.asl>
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
 }