[S] Change in coreboot[main]: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Maximilian Brune, Paul Menzel.

Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email )

Change subject: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet
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Patch Set 4: Code-Review+2

(2 comments)

Patchset:

PS4: 
apart from the open comment about the register names in the commit message, this looks god to me

Commit Message:

https://review.coreboot.org/c/coreboot/+/84574/comment/76fb6760_6df76bb5?usp... :
PS4, Line 9: MISC2/3
> 1/2 or is my math wrong?  Otherwise the patch LGTM.

yes, MISC1 and MISC2. those 4 registers are counted in a really weird way though: MISC, MISC0, MISC1 and MISC2