Change in coreboot[master]: cpu/intel/socket_LGA775: Use common CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23470

Change subject: cpu/intel/socket_LGA775: Use common CAR
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cpu/intel/socket_LGA775: Use common CAR

This code will most likely not work on Intel Netburst CPUs but there
are reports that these don't work anyway and on some boards Netburst
CPUs don't even get to output a post_code (even if placed very early
on, after entering 32bit protected mode).

Change-Id: I6bf2fe603b4458f14fb7cfaa55d68ebf6d75b347
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_LGA775/Makefile.inc
2 files changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/23470/1

diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..a965d13 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -6,14 +6,15 @@
 config SOCKET_SPECIFIC_OPTIONS # dummy
    def_bool y
    select CPU_INTEL_MODEL_6FX
-	select CPU_INTEL_MODEL_F3X
-	select CPU_INTEL_MODEL_F4X
+	select CPU_INTEL_MODEL_F3X # Probably not working
+	select CPU_INTEL_MODEL_F4X # Probably not working
 #	select CPU_INTEL_MODEL_F6X
 #	select CPU_INTEL_MODEL_1066X
    select CPU_INTEL_MODEL_1067X
    select MMX
    select SSE
    select SIPI_VECTOR_IN_ROM
+	select CPU_INTEL_COMMON_CAR

config DCACHE_RAM_SIZE
    hex
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index ffcd1cb..b53d9af 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -13,6 +13,6 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+subdirs-y += ../car
 romstage-y += ../car/romstage.c
 romstage-y += ../car/romstage.c