Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56256 )
Change subject: soc/intel/*: Allow configuring 8254 timer via CMOS ......................................................................
soc/intel/*: Allow configuring 8254 timer via CMOS
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used.
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 7 files changed, 32 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 489935d..f6a88ec 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -8,6 +8,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> @@ -21,6 +22,7 @@ #include <soc/soc_chip.h> #include <stdlib.h> #include <string.h> +#include <types.h>
/* THC assignment definition */ #define THC_NONE 0 @@ -533,8 +535,9 @@ const struct soc_intel_alderlake_config *config) { /* Legacy 8254 timer support */ - s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + s_cfg->Enable8254ClockGating = !use_8254; + s_cfg->Enable8254ClockGatingOnS3 = !use_8254; }
static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9d2d722..0924763 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/power_limit.h> @@ -17,6 +18,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> +#include <types.h>
#include "chip.h"
@@ -425,8 +427,9 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + params->Enable8254ClockGating = !use_8254; + params->Enable8254ClockGatingOnS3 = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 31d987a..ae9584c 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -5,6 +5,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/pmclib.h> #include <intelblocks/xdci.h> @@ -14,6 +15,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h>
/* SATA DEVSLP idle timeout default values */ #define DEF_DMVAL 15 @@ -159,7 +161,8 @@ params->PavpEnable = 0;
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = 1;
/* PCH Master Gating Control */ diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index aee2ef8..ba40f3f 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -5,6 +5,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -12,6 +13,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h> #include <fsp/ppi/mp_service_ppi.h>
static void parse_devicetree(FSP_S_CONFIG *params) @@ -92,8 +94,9 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + params->Enable8254ClockGating = !use_8254; + params->Enable8254ClockGatingOnS3 = !use_8254;
/* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 4ec9294..d68494f 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -5,6 +5,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/pmclib.h> #include <intelblocks/xdci.h> @@ -14,6 +15,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h>
/* * ME End of Post configuration @@ -84,7 +86,8 @@ params->EndOfPostMessage = EOP_DISABLE;
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = 1;
/* disable Legacy PME */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 354a6ee..3979911 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -9,6 +9,7 @@ #include <device/pci_ids.h> #include <fsp/util.h> #include <gpio.h> +#include <option.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> @@ -28,6 +29,7 @@ #include <soc/systemagent.h> #include <soc/usb.h> #include <string.h> +#include <types.h>
#include "chip.h"
@@ -340,7 +342,8 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + params->Early8254ClockGatingEnable = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index d8f92ae..010ff02 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -11,6 +11,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> @@ -26,6 +27,7 @@ #include <soc/soc_chip.h> #include <soc/tcss.h> #include <string.h> +#include <types.h>
/* THC assignment definition */ #define THC_NONE 0 @@ -547,8 +549,9 @@ params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + params->Enable8254ClockGating = !use_8254; + params->Enable8254ClockGatingOnS3 = !use_8254;
/* Enable Hybrid storage auto detection */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
-
Paul Fagerburg (Code Review)