[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add SPI configuration

[Jakub Czapiga (Code Review)]

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli.

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75577?usp=email )

Change subject: mb/google/rex/variants/ovis: Add SPI configuration
......................................................................

mb/google/rex/variants/ovis: Add SPI configuration

BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis

Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7
Signed-off-by: Jakub Czapiga 
---
M src/mainboard/google/rex/variants/ovis/overridetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/75577/1

diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb
index bc10cd1..1ec938e 100644
--- a/src/mainboard/google/rex/variants/ovis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb
@@ -1,5 +1,11 @@
 chip soc/intel/meteorlake

+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+	}"
+
    register "serial_io_i2c_mode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
@@ -43,5 +49,10 @@
    			device i2c 50 on end
    		end
    	end
+		device ref soc_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
    end
 end