[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email )

Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................

Patch Set 4:

(1 comment)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/78327/comment/458863f0_7f6e8bb9 :
PS4, Line 112: 	.scan_bus = non_iio_pci_domain_scan_bus,
> Don't these integrated devices implement the upper layers of PCI (i.e. show as a […]

yeah ... integrated_iio_stack_... is a good idea.

P.S. these devices are integrated and logically PCI devices, but there is no physical PCI PHY between them and the core.