Change in coreboot[master]: soc/amd/common: Collect timestamps before and after AGESA calls

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22798

Change subject: soc/amd/common: Collect timestamps before and after AGESA calls
......................................................................

soc/amd/common: Collect timestamps before and after AGESA calls

BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.

Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be
Signed-off-by: Martin Roth 
---
M src/soc/amd/common/agesawrapper.c
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/22798/1

diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c
index b939183..6d8796c 100644
--- a/src/soc/amd/common/agesawrapper.c
+++ b/src/soc/amd/common/agesawrapper.c
@@ -20,6 +20,7 @@
 #include <cpu/x86/mtrr.h>
 #include <BiosCallOuts.h>
 #include <string.h>
+#include <timestamp.h>

void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {}
 void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}
@@ -62,7 +63,10 @@
    AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));
    AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);

+	timestamp_add_now(TS_AGESA_INIT_RESET_START);
    status = AmdInitReset(&AmdResetParams);
+	timestamp_add_now(TS_AGESA_INIT_RESET_DONE);
+
    if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
    AmdReleaseStruct (&AmdParamStruct);
    return status;
@@ -88,7 +92,10 @@
    OemCustomizeInitEarly (AmdEarlyParamsPtr);

AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled;
+
+	timestamp_add_now(TS_AGESA_INIT_EARLY_START);
    status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	timestamp_add_now(TS_AGESA_INIT_EARLY_DONE);

if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
    AmdReleaseStruct (&AmdParamStruct);
@@ -127,7 +134,9 @@
    	"unknown"
    );

+	timestamp_add_now(TS_AGESA_INIT_POST_START);
    status = AmdInitPost (PostParams);
+	timestamp_add_now(TS_AGESA_INIT_POST_DONE);

/* If UMA is enabled we currently have it below TOP_MEM as well.
     * UMA may or may not be cacheable, so Sub4GCacheTop could be
@@ -189,7 +198,10 @@
    EnvParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3);
    EnvParam->GnbEnvConfiguration.IommuSupport = FALSE;

+	timestamp_add_now(TS_AGESA_INIT_ENV_START);
    status = AmdInitEnv (EnvParam);
+	timestamp_add_now(TS_AGESA_INIT_ENV_DONE);
+
    if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
    /* Initialize Subordinate Bus Number and Secondary Bus Number
     * In platform BIOS this address is allocated by PCI enumeration code
@@ -257,7 +269,10 @@
    MidParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);
    MidParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3);

+	timestamp_add_now(TS_AGESA_INIT_MID_START);
    status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	timestamp_add_now(TS_AGESA_INIT_MID_DONE);
+
    if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
    AmdReleaseStruct (&AmdParamStruct);

@@ -284,7 +299,11 @@
    /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
    AmdCreateStruct(&AmdParamStruct);
    AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+
+	timestamp_add_now(TS_AGESA_INIT_LATE_START);
    Status = AmdInitLate(AmdLateParams);
+	timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
+
    if (Status != AGESA_SUCCESS) {
    	agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);
    	ASSERT(Status == AGESA_SUCCESS);