Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14972
-gerrit
commit 7bcf8c2a13ef8b16c6b93d694dd86bbf08adc466 Author: Aaron Durbin adurbin@chromium.org Date: Thu May 26 11:00:44 2016 -0500
soc/intel/apollolake: add support for verstage
There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification.
Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/apollolake/Kconfig | 6 ++++++ src/soc/intel/apollolake/Makefile.inc | 6 ++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 6 ++++++ src/soc/intel/apollolake/pmutil.c | 12 ++++++++++++ 4 files changed, 30 insertions(+)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..d6c5ffc 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -123,6 +123,12 @@ config ROMSTAGE_ADDR help The base address (in CAR) where romstage should be linked
+config VERSTAGE_ADDR + hex + default 0xfef60000 + help + The base address (in CAR) where verstage should be linked + config CACHE_MRC_SETTINGS bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 80617a7..b8f0c18 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -56,6 +56,12 @@ postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c
+verstage-y += memmap.c +verstage-y += mmap_boot.c +verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +verstage-y += tsc_freq.c +verstage-y += pmutil.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
# Since FSP-M runs in CAR we need to relocate it to a specific address diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8279432..b8d6f22 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -67,6 +67,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ /* Decode the ACPI I/O port range for early firmware verification.*/ + dev = PMC_DEV; + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MASTER); + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo); } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a04..9340ba5 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -26,6 +26,7 @@ #include <soc/pm.h> #include <device/device.h> #include <device/pci.h> +#include <vendorcode/google/chromeos/vboot_common.h>
static uintptr_t read_pmc_mmio_bar(void) { @@ -336,3 +337,14 @@ int fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps->prev_sleep_state; } + +int vboot_platform_is_resuming(void) +{ + int typ; + + if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) + return 0; + + typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; + return typ == SLP_TYP_S3; +}
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Aaron Durbin