Patch set updated for coreboot: drivers/intel/fsp1_1: Do no run microcode updates via FSP
Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11463
-gerrit
commit cc7a12a0eae9ffd7f144576da494fb00bc5c3938 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sat Aug 29 14:34:25 2015 -0700
drivers/intel/fsp1_1: Do no run microcode updates via FSP
Our bootblock already upgrades the CPU microcode before any call to FSP. As a result, the FSP microcode update will be a no-op.
Since we have to pass the microcode location to FSP via a stack, before CAR, this stack exists in flash, and needs the location hardcoded. If we remove this limitation, then we no longer need to hardcode the location of the microcode, and can use the standard rules for adding microcode. Note that this is only true for the BSP. APs take a different path.
TEST=Build cyan and observe BSP come up with updated microcode (rev > 0), and observed APs are also succesfully updated, Then booted Fedora 22 with linux-4.2-rc8 and SeaBIOS payload.
Change-Id: I47d11061a1cfb741a633102225b63715d1bfd382 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/drivers/intel/fsp1_1/Kconfig | 13 ------------- src/drivers/intel/fsp1_1/cache_as_ram.inc | 18 +++++++++++++++--- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 15 insertions(+), 38 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 2ffa323..cdf767d 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -45,19 +45,6 @@ config HAVE_FSP_BIN
if HAVE_FSP_BIN
-config CPU_MICROCODE_CBFS_LEN - hex "Microcode update region length in bytes" - default 0 - help - The length in bytes of the microcode update region. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode update base address in CBFS" - default 0 - help - The location (base address) in CBFS that contains the microcode update - binary. - config FSP_FILE string "Intel FSP binary path and filename" help diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6af30ce..3ef8cb7 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -33,6 +33,8 @@ #include <cpu/x86/post_code.h> #include <cbmem.h>
+#define FSP_SUCCESS 0 +#define FSP_INVALID_PARAMETER 2 #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
/* @@ -109,9 +111,19 @@ CAR_init_done: * mm1: high 32-bits of TSC value */
- cmp $0, %eax + cmp $FSP_SUCCESS, %eax + je fsp_temp_ram_init_ok + + /* + * It's OK if we get FSP_INVALID_PARAMETER. In most cases, that means + * that a microcode update was not found (because we never passed one + * to FSP in the first place). However CAR setup is still done. + */ + cmp $FSP_INVALID_PARAMETER, %al jne halt2
+fsp_temp_ram_init_ok: + /* Setup bootloader stack */ movl %edx, %esp
@@ -344,8 +356,8 @@ fake_fsp_stack: .long find_fsp_ret
CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */ .long CONFIG_CBFS_SIZE /* Total Firmware Length */
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -
-
Alexandru Gagniuc