Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998
-gerrit
commit 5cfa66fcd058d797f16511817660c2192a2d47dd Author: Arthur Heymans arthur@aheymans.xyz Date: Fri Dec 30 21:07:18 2016 +0100
nb/intel/x4x: Implement resume from S3 suspend
It rewrites the results of receive enable stored in the upper nvram region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers. (Not enforcing a reset here, since 0 does not necessarily mean it's not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +++++-- src/northbridge/intel/x4x/pcie.c | 15 ++++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 28 ++++++++++++++++++++------ src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME
config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d76fbb2..0a1470b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume;
/* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist)
x4x_early_init();
+ s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n");
- x4x_late_init(); + x4x_late_init(s3_resume);
printk(BIOS_DEBUG, "x4x late init complete\n");
diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h"
@@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); }
-void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 48a46fa..f1ae3fc 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -262,6 +262,16 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; + u32 pmsts = MCHBAR32(PMSTS_MCHBAR); + + if (s->boot_path >= 1) { + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + }
pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
@@ -1476,7 +1486,6 @@ static void rcven_ddr2(struct sysinfo *s) readdelay[ch] = MCHBAR16(0x400*ch + 0x588); } // END EACH POPULATED CHANNEL
- /* TODO: Resume support using this */ FOR_EACH_CHANNEL(ch) { for (lane = 0; lane < 8; lane++) { MCHBAR8(0x400*ch + 0x560 + (lane*4)) = @@ -1556,7 +1565,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2);
/* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_WARM_RESET) { + if ((s->boot_path == BOOT_PATH_WARM_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2044,7 +2054,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n");
// JEDEC reset - jedec_ddr2(s); + if (s->boot_path != BOOT_PATH_SUSPEND) + jedec_ddr2(s);
printk(BIOS_DEBUG, "Done jedec steps\n");
@@ -2095,13 +2106,18 @@ void raminit_ddr2(struct sysinfo *s) volatile u32 data; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); write32((u32 *)reg32, 0xffffffff); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); write32((u32 *)reg32, 0x00000000); data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); } } } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 66d765a..faae775 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals {
#ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);
-
Arthur Heymans