Attention is currently required from: Maximilian Brune, Paul Menzel.
Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/amd/glinda/.../iomap.h: Update for glinda ......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84380/comment/9f871d5c_222385eb?usp... : PS4, Line 10: DMA4 apparently doesn't exist anymore so remove it. no; it's just not visible in the ppr version you have access to :(
File src/soc/amd/glinda/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/84380/comment/8cfc08fd_1fdb1b4c?usp... : PS4, Line 35: #define APU_DMAC4_BASE 0xfedd0000 this is still there; just not visible in the non-internal ppr. also there's always one dmac per uart, so having UART4, but not DMAC4 doesn't seem right
File src/soc/amd/glinda/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/84380/comment/37ca20a1_11f4e8d3?usp... : PS1, Line 33: #define APU_UART4_BASE 0xfedd1000 //TODO not in the table but used on actual schematics (does it exist or not?)
I was looking at table 147 in document 57254 (Rev 1.59) and I can't see UART4 there. […]
please mention the name of the table; the table number isn't helpful for me, since i'm looking at the internal version and not the more or less redacted one which has other table numbers due to less things being visible. is that the "Address Space Mapping under APB BUS" table? if that table and the register descriptions disagree, i'd much rather trust the register descriptions than that table
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Felix Held (Code Review)