[S] Change in coreboot[main]: mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84264?usp=email )

Change subject: mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs
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mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs

Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
1 file changed, 3 insertions(+), 7 deletions(-)

Approvals:
  Felix Held: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index df8bd99..0070f22 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -1,7 +1,8 @@
 chip soc/intel/cannonlake
-	# CPU
-	# Enable Enhanced Intel SpeedStep
+	# FSP UPDs
    register "eist_enable"			= "true"
+	register "enable_c6dram"		= "1"
+	register "SaGv"				= "SaGv_Enabled"

# Graphics
    # IGD Displays
@@ -14,11 +15,6 @@
    	.backlight_pwm_hz		=  200,				// PWM
    }"

-	# FSP Memory
-	register "enable_c6dram"		= "1"
-	register "SaGv"				= "SaGv_Enabled"
-
-	# FSP Silicon
    # Serial I/O
    register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]		= PchSerialIoPci,