Patch set updated for coreboot: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17597

-gerrit

commit 60178325e77bfa0a925b8f20d5008e1e463b788e
Author: Arthur Heymans 
Date:   Thu Nov 24 13:23:05 2016 +0100

nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency

This allows to set the backlight PWM frequency and the
    duty cycle in the devicetree instead of using a plain BLC_PWM_CTL
    value.

Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3
    Signed-off-by: Arthur Heymans 
---
 src/northbridge/intel/gm45/chip.h |  2 ++
 src/northbridge/intel/gm45/gma.c  | 22 ++++++++++++++++++++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index 836d6bb..a281ee9 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -26,6 +26,8 @@ struct northbridge_intel_gm45_config {
    u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
    u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
    struct i915_gpu_controller_info gfx;
+	u16 pwm_freq;
+	u8 duty_cycle;

/*
     * Maximum PCI mmio size in MiB.
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 3e9f508..37f81c5 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -629,11 +629,25 @@ static u32 get_cdclk(struct device *const dev)
    }
 }

+static u32 freq_to_blc_pwm_ctl(struct device *const dev,
+			u16 pwm_freq, u8 duty_perc)
+{
+	u32 blc_mod;
+
+	blc_mod = get_cdclk(dev) / (128 * pwm_freq);
+
+	if (duty_perc <= 100)
+		return (blc_mod << 16) | (blc_mod * duty_perc / 100);
+	else
+		return (blc_mod << 16) | blc_mod;
+}
+
 static void gma_pm_init_post_vbios(struct device *const dev)
 {
    const struct northbridge_intel_gm45_config *const conf = dev->chip_info;

u32 reg32;
+	u8 reg8;

/* Setup Panel Power On Delays */
    reg32 = gtt_read(PP_ON_DELAYS);
@@ -661,10 +675,14 @@ static void gma_pm_init_post_vbios(struct device *const dev)

/* Enable Backlight  */
    gtt_write(BLC_PWM_CTL2, (1 << 31));
-	if (conf->gfx.backlight == 0)
+	reg8 = 100;
+	if (conf->duty_cycle != 0)
+		reg8 = conf->duty_cycle;
+	if (conf->pwm_freq == 0)
    	gtt_write(BLC_PWM_CTL, 0x06100610);
    else
-		gtt_write(BLC_PWM_CTL, conf->gfx.backlight);
+		gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev,
+						conf->pwm_freq,	reg8));
 }

static void gma_func0_init(struct device *dev)