Change in coreboot[master]: soc/amd/common/lpc/espi_util: move register definitions to header file

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60770 )

Change subject: soc/amd/common/lpc/espi_util: move register definitions to header file
......................................................................

soc/amd/common/lpc/espi_util: move register definitions to header file

Define the register offsets and bits in a separate header file instead
of in the middle of the .c file.

Signed-off-by: Felix Held 
Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25
---
A src/soc/amd/common/block/lpc/espi_def.h
M src/soc/amd/common/block/lpc/espi_util.c
2 files changed, 56 insertions(+), 48 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/60770/1

diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h
new file mode 100644
index 0000000..a14f10f
--- /dev/null
+++ b/src/soc/amd/common/block/lpc/espi_def.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_ESPI_DEF_H
+#define AMD_BLOCK_ESPI_DEF_H
+
+#define ESPI_DN_TX_HDR0			0x00
+#define ESPI_DN_TX_HDR1			0x04
+#define ESPI_DN_TX_HDR2			0x08
+#define ESPI_DN_TX_DATA			0x0c
+
+#define ESPI_MASTER_CAP			0x2c
+#define  ESPI_VW_MAX_SIZE_SHIFT		13
+#define  ESPI_VW_MAX_SIZE_MASK		(0x3f << ESPI_VW_MAX_SIZE_SHIFT)
+
+#define ESPI_GLOBAL_CONTROL_0		0x30
+#define  ESPI_WAIT_CNT_SHIFT		24
+#define  ESPI_WAIT_CNT_MASK		(0x3f << ESPI_WAIT_CNT_SHIFT)
+#define  ESPI_WDG_CNT_SHIFT		8
+#define  ESPI_WDG_CNT_MASK		(0xffff << ESPI_WDG_CNT_SHIFT)
+#define  ESPI_AL_IDLE_TIMER_SHIFT	4
+#define  ESPI_AL_IDLE_TIMER_MASK	(0x7 << ESPI_AL_IDLE_TIMER_SHIFT)
+#define  ESPI_AL_STOP_EN		(1 << 3)
+#define  ESPI_PR_CLKGAT_EN		(1 << 2)
+#define  ESPI_WAIT_CHKEN		(1 << 1)
+#define  ESPI_WDG_EN			(1 << 0)
+
+#define ESPI_GLOBAL_CONTROL_1		0x34
+#define  ESPI_RGCMD_INT_MAP_SHIFT	13
+#define  ESPI_RGCMD_INT_MAP_MASK	(0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
+#define    ESPI_RGCMD_INT(irq)		((irq) << ESPI_RGCMD_INT_MAP_SHIFT)
+#define    ESPI_RGCMD_INT_SMI		(0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
+#define  ESPI_ERR_INT_MAP_SHIFT		8
+#define  ESPI_ERR_INT_MAP_MASK		(0x1f << ESPI_ERR_INT_MAP_SHIFT)
+#define    ESPI_ERR_INT(irq)		((irq) << ESPI_ERR_INT_MAP_SHIFT)
+#define    ESPI_ERR_INT_SMI		(0x1f << ESPI_ERR_INT_MAP_SHIFT)
+#define  ESPI_SUB_DECODE_SLV_SHIFT	3
+#define  ESPI_SUB_DECODE_SLV_MASK	(0x3 << ESPI_SUB_DECODE_SLV_SHIFT)
+#define  ESPI_SUB_DECODE_EN		(1 << 2)
+#define  ESPI_BUS_MASTER_EN		(1 << 1)
+#define  ESPI_SW_RST			(1 << 0)
+
+#define ESPI_SLAVE0_INT_EN		0x6c
+#define ESPI_SLAVE0_INT_STS		0x70
+#define  ESPI_STATUS_DNCMD_COMPLETE	(1 << 28)
+#define  ESPI_STATUS_NON_FATAL_ERROR	(1 << 6)
+#define  ESPI_STATUS_FATAL_ERROR	(1 << 5)
+#define  ESPI_STATUS_NO_RESPONSE	(1 << 4)
+#define  ESPI_STATUS_CRC_ERR		(1 << 2)
+#define  ESPI_STATUS_WAIT_TIMEOUT	(1 << 1)
+#define  ESPI_STATUS_BUS_ERROR		(1 << 0)
+
+#define ESPI_RXVW_POLARITY		0xac
+
+#endif /* AMD_BLOCK_ESPI_DEF_H */
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index f36f778..1e5b5d0 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -10,6 +10,8 @@
 #include <timer.h>
 #include <types.h>

+#include <espi_def.h>
+
 static uintptr_t espi_bar;

void espi_update_static_bar(uintptr_t bar)
@@ -315,7 +317,6 @@
    return CB_SUCCESS;
 }

-#define ESPI_DN_TX_HDR0			0x00
 enum espi_cmd_type {
    CMD_TYPE_SET_CONFIGURATION = 0,
    CMD_TYPE_GET_CONFIGURATION = 1,
@@ -326,53 +327,6 @@
    CMD_TYPE_FLASH = 7,
 };

-#define ESPI_DN_TX_HDR1				0x04
-#define ESPI_DN_TX_HDR2				0x08
-#define ESPI_DN_TX_DATA				0x0c
-
-#define ESPI_MASTER_CAP				0x2c
-#define  ESPI_VW_MAX_SIZE_SHIFT			13
-#define  ESPI_VW_MAX_SIZE_MASK			(0x3f << ESPI_VW_MAX_SIZE_SHIFT)
-
-#define ESPI_GLOBAL_CONTROL_0			0x30
-#define  ESPI_WAIT_CNT_SHIFT			24
-#define  ESPI_WAIT_CNT_MASK			(0x3f << ESPI_WAIT_CNT_SHIFT)
-#define  ESPI_WDG_CNT_SHIFT			8
-#define  ESPI_WDG_CNT_MASK			(0xffff << ESPI_WDG_CNT_SHIFT)
-#define  ESPI_AL_IDLE_TIMER_SHIFT		4
-#define  ESPI_AL_IDLE_TIMER_MASK		(0x7 << ESPI_AL_IDLE_TIMER_SHIFT)
-#define  ESPI_AL_STOP_EN			(1 << 3)
-#define  ESPI_PR_CLKGAT_EN			(1 << 2)
-#define  ESPI_WAIT_CHKEN			(1 << 1)
-#define  ESPI_WDG_EN				(1 << 0)
-
-#define ESPI_GLOBAL_CONTROL_1			0x34
-#define  ESPI_RGCMD_INT_MAP_SHIFT		13
-#define  ESPI_RGCMD_INT_MAP_MASK		(0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
-#define    ESPI_RGCMD_INT(irq)			((irq) << ESPI_RGCMD_INT_MAP_SHIFT)
-#define    ESPI_RGCMD_INT_SMI			(0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
-#define  ESPI_ERR_INT_MAP_SHIFT			8
-#define  ESPI_ERR_INT_MAP_MASK			(0x1f << ESPI_ERR_INT_MAP_SHIFT)
-#define    ESPI_ERR_INT(irq)			((irq) << ESPI_ERR_INT_MAP_SHIFT)
-#define    ESPI_ERR_INT_SMI			(0x1f << ESPI_ERR_INT_MAP_SHIFT)
-#define  ESPI_SUB_DECODE_SLV_SHIFT		3
-#define  ESPI_SUB_DECODE_SLV_MASK		(0x3 << ESPI_SUB_DECODE_SLV_SHIFT)
-#define  ESPI_SUB_DECODE_EN			(1 << 2)
-#define  ESPI_BUS_MASTER_EN			(1 << 1)
-#define  ESPI_SW_RST				(1 << 0)
-
-#define ESPI_SLAVE0_INT_EN			0x6c
-#define ESPI_SLAVE0_INT_STS			0x70
-#define  ESPI_STATUS_DNCMD_COMPLETE		(1 << 28)
-#define  ESPI_STATUS_NON_FATAL_ERROR		(1 << 6)
-#define  ESPI_STATUS_FATAL_ERROR		(1 << 5)
-#define  ESPI_STATUS_NO_RESPONSE		(1 << 4)
-#define  ESPI_STATUS_CRC_ERR			(1 << 2)
-#define  ESPI_STATUS_WAIT_TIMEOUT		(1 << 1)
-#define  ESPI_STATUS_BUS_ERROR			(1 << 0)
-
-#define ESPI_RXVW_POLARITY			0xac
-
 #define ESPI_CMD_TIMEOUT_US			100
 #define ESPI_CH_READY_TIMEOUT_US		10000